drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/samsung/sxgbe/sxgbe_reg.h
Extension
.h
Size
20116 bytes
Lines
489
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SXGBE_REGMAP_H__
#define __SXGBE_REGMAP_H__

/* SXGBE MAC Registers */
#define SXGBE_CORE_TX_CONFIG_REG	0x0000
#define SXGBE_CORE_RX_CONFIG_REG	0x0004
#define SXGBE_CORE_PKT_FILTER_REG	0x0008
#define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
#define SXGBE_CORE_HASH_TABLE_REG0	0x0010
#define SXGBE_CORE_HASH_TABLE_REG1	0x0014
#define SXGBE_CORE_HASH_TABLE_REG2	0x0018
#define SXGBE_CORE_HASH_TABLE_REG3	0x001C
#define SXGBE_CORE_HASH_TABLE_REG4	0x0020
#define SXGBE_CORE_HASH_TABLE_REG5	0x0024
#define SXGBE_CORE_HASH_TABLE_REG6	0x0028
#define SXGBE_CORE_HASH_TABLE_REG7	0x002C

/* EEE-LPI Registers */
#define SXGBE_CORE_LPI_CTRL_STATUS	0x00D0
#define SXGBE_CORE_LPI_TIMER_CTRL	0x00D4

/* VLAN Specific Registers */
#define SXGBE_CORE_VLAN_TAG_REG		0x0050
#define SXGBE_CORE_VLAN_HASHTAB_REG	0x0058
#define SXGBE_CORE_VLAN_INSCTL_REG	0x0060
#define SXGBE_CORE_VLAN_INNERCTL_REG	0x0064
#define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C

/* Flow Contol Registers */
#define SXGBE_CORE_TX_Q0_FLOWCTL_REG	0x0070
#define SXGBE_CORE_TX_Q1_FLOWCTL_REG	0x0074
#define SXGBE_CORE_TX_Q2_FLOWCTL_REG	0x0078
#define SXGBE_CORE_TX_Q3_FLOWCTL_REG	0x007C
#define SXGBE_CORE_TX_Q4_FLOWCTL_REG	0x0080
#define SXGBE_CORE_TX_Q5_FLOWCTL_REG	0x0084
#define SXGBE_CORE_TX_Q6_FLOWCTL_REG	0x0088
#define SXGBE_CORE_TX_Q7_FLOWCTL_REG	0x008C
#define SXGBE_CORE_RX_FLOWCTL_REG	0x0090
#define SXGBE_CORE_RX_CTL0_REG		0x00A0
#define SXGBE_CORE_RX_CTL1_REG		0x00A4
#define SXGBE_CORE_RX_CTL2_REG		0x00A8
#define SXGBE_CORE_RX_CTL3_REG		0x00AC

#define SXGBE_CORE_RXQ_ENABLE_MASK	0x0003
#define SXGBE_CORE_RXQ_ENABLE		0x0002
#define SXGBE_CORE_RXQ_DISABLE		0x0000

/* Interrupt Registers */
#define SXGBE_CORE_INT_STATUS_REG	0x00B0
#define SXGBE_CORE_INT_ENABLE_REG	0x00B4
#define SXGBE_CORE_RXTX_ERR_STATUS_REG	0x00B8
#define SXGBE_CORE_PMT_CTL_STATUS_REG	0x00C0
#define SXGBE_CORE_RWK_PKT_FILTER_REG	0x00C4
#define SXGBE_CORE_VERSION_REG		0x0110
#define SXGBE_CORE_DEBUG_REG		0x0114
#define SXGBE_CORE_HW_FEA_REG(index)	(0x011C + index * 4)

/* SMA(MDIO) module registers */
#define SXGBE_MDIO_SCMD_ADD_REG		0x0200
#define SXGBE_MDIO_SCMD_DATA_REG	0x0204
#define SXGBE_MDIO_CCMD_WADD_REG	0x0208
#define SXGBE_MDIO_CCMD_WDATA_REG	0x020C
#define SXGBE_MDIO_CSCAN_PORT_REG	0x0210
#define SXGBE_MDIO_INT_STATUS_REG	0x0214
#define SXGBE_MDIO_INT_ENABLE_REG	0x0218
#define SXGBE_MDIO_PORT_CONDCON_REG	0x021C
#define SXGBE_MDIO_CLAUSE22_PORT_REG	0x0220

/* port specific, addr = 0-3 */
#define SXGBE_MDIO_DEV_BASE_REG		0x0230
#define SXGBE_MDIO_PORT_DEV_REG(addr)			\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0)
#define SXGBE_MDIO_PORT_LSTATUS_REG(addr)		\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4)
#define SXGBE_MDIO_PORT_ALIVE_REG(addr)			\
	(SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8)

#define SXGBE_CORE_GPIO_CTL_REG		0x0278
#define SXGBE_CORE_GPIO_STATUS_REG	0x027C

/* Address registers for filtering */
#define SXGBE_CORE_ADD_BASE_REG		0x0300

/* addr = 0-31 */
#define SXGBE_CORE_ADD_HIGHOFFSET(addr)			\
	(SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0)
#define SXGBE_CORE_ADD_LOWOFFSET(addr)			\
	(SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4)

/* SXGBE MMC registers */

Annotation

Implementation Notes