drivers/net/ethernet/sfc/ef10_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/sfc/ef10_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/sfc/ef10_regs.h
Extension
.h
Size
14633 bytes
Lines
438
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef EFX_EF10_REGS_H
#define EFX_EF10_REGS_H

/* EF10 hardware architecture definitions have a name prefix following
 * the format:
 *
 *     E<type>_<min-rev><max-rev>_
 *
 * The following <type> strings are used:
 *
 *             MMIO register  Host memory structure
 * -------------------------------------------------------------
 * Address     R
 * Bitfield    RF             SF
 * Enumerator  FE             SE
 *
 * <min-rev> is the first revision to which the definition applies:
 *
 *     D: Huntington A0
 *
 * If the definition has been changed or removed in later revisions
 * then <max-rev> is the last revision to which the definition applies;
 * otherwise it is "Z".
 */

/**************************************************************************
 *
 * EF10 registers and descriptors
 *
 **************************************************************************
 */

/* BIU_HW_REV_ID_REG:  */
#define	ER_DZ_BIU_HW_REV_ID 0x00000000
#define	ERF_DZ_HW_REV_ID_LBN 0
#define	ERF_DZ_HW_REV_ID_WIDTH 32

/* BIU_MC_SFT_STATUS_REG:  */
#define	ER_DZ_BIU_MC_SFT_STATUS 0x00000010
#define	ER_DZ_BIU_MC_SFT_STATUS_STEP 4
#define	ER_DZ_BIU_MC_SFT_STATUS_ROWS 8
#define	ERF_DZ_MC_SFT_STATUS_LBN 0
#define	ERF_DZ_MC_SFT_STATUS_WIDTH 32

/* BIU_INT_ISR_REG:  */
#define	ER_DZ_BIU_INT_ISR 0x00000090
#define	ERF_DZ_ISR_REG_LBN 0
#define	ERF_DZ_ISR_REG_WIDTH 32

/* MC_DB_LWRD_REG:  */
#define	ER_DZ_MC_DB_LWRD 0x00000200
#define	ERF_DZ_MC_DOORBELL_L_LBN 0
#define	ERF_DZ_MC_DOORBELL_L_WIDTH 32

/* MC_DB_HWRD_REG:  */
#define	ER_DZ_MC_DB_HWRD 0x00000204
#define	ERF_DZ_MC_DOORBELL_H_LBN 0
#define	ERF_DZ_MC_DOORBELL_H_WIDTH 32

/* EVQ_RPTR_REG:  */
#define	ER_DZ_EVQ_RPTR 0x00000400
#define	ER_DZ_EVQ_RPTR_STEP 8192
#define	ER_DZ_EVQ_RPTR_ROWS 2048
#define	ERF_DZ_EVQ_RPTR_VLD_LBN 15
#define	ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
#define	ERF_DZ_EVQ_RPTR_LBN 0
#define	ERF_DZ_EVQ_RPTR_WIDTH 15

/* EVQ_TMR_REG:  */
#define	ER_DZ_EVQ_TMR 0x00000420
#define	ER_DZ_EVQ_TMR_STEP 8192
#define	ER_DZ_EVQ_TMR_ROWS 2048
#define	ERF_FZ_TC_TMR_REL_VAL_LBN 16
#define	ERF_FZ_TC_TMR_REL_VAL_WIDTH 14
#define	ERF_DZ_TC_TIMER_MODE_LBN 14
#define	ERF_DZ_TC_TIMER_MODE_WIDTH 2
#define	ERF_DZ_TC_TIMER_VAL_LBN 0
#define	ERF_DZ_TC_TIMER_VAL_WIDTH 14

/* RX_DESC_UPD_REG:  */
#define	ER_DZ_RX_DESC_UPD 0x00000830
#define	ER_DZ_RX_DESC_UPD_STEP 8192
#define	ER_DZ_RX_DESC_UPD_ROWS 2048
#define	ERF_DZ_RX_DESC_WPTR_LBN 0
#define	ERF_DZ_RX_DESC_WPTR_WIDTH 12

/* TX_DESC_UPD_REG:  */
#define	ER_DZ_TX_DESC_UPD 0x00000a10
#define	ER_DZ_TX_DESC_UPD_STEP 8192
#define	ER_DZ_TX_DESC_UPD_ROWS 2048

Annotation

Implementation Notes