drivers/net/ethernet/sis/sis900.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/sis/sis900.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/sis/sis900.h
Extension: .h
Size: 10788 bytes
Lines: 331
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

enum sis900_registers
enum sis900_command_register_bits
enum sis900_configuration_register_bits
enum sis900_eeprom_access_register_bits
enum sis900_interrupt_register_bits
enum sis900_interrupt_enable_register_bits
enum sis900_tx_rx_dma
enum sis900_transmit_config_register_bits
enum sis900_reveive_config_register_bits
enum sis900_receive_filter_control_register_bits
enum sis900_reveive_filter_data_mask
enum sis900_eeprom_address
enum sis900_eeprom_command
enum sis96x_eeprom_command
enum sis900_pci_registers
enum sis900_cfgpmc_register_bits
enum sis900_pmesp_bits
enum sis900_cfgpmcsr_register_bits
enum sis900_power_management_control_register_bits
enum sis900_buffer_status
enum sis900_tx_buffer_status
enum sis900_rx_buffer_status
enum mii_registers
enum sis_mii_registers
enum ics_mii_registers
enum amd_mii_registers
enum mii_control_register_bits
enum mii_status_register_bits
enum mii_nway_register_bits
enum mii_stsout_register_bits
enum mii_stsics_register_bits
enum mii_stssum_register_bits
enum sis900_revision_id
enum sis630_revision_id

Annotated Snippet

#define SIS900_TOTAL_SIZE 0x100

/* Symbolic offsets to registers. */
enum sis900_registers {
	cr=0x0,                 //Command Register
	cfg=0x4,                //Configuration Register
	mear=0x8,               //EEPROM Access Register
	ptscr=0xc,              //PCI Test Control Register
	isr=0x10,               //Interrupt Status Register
	imr=0x14,               //Interrupt Mask Register
	ier=0x18,               //Interrupt Enable Register
	epar=0x18,              //Enhanced PHY Access Register
	txdp=0x20,              //Transmit Descriptor Pointer Register
        txcfg=0x24,             //Transmit Configuration Register
        rxdp=0x30,              //Receive Descriptor Pointer Register
        rxcfg=0x34,             //Receive Configuration Register
        flctrl=0x38,            //Flow Control Register
        rxlen=0x3c,             //Receive Packet Length Register
        rfcr=0x48,              //Receive Filter Control Register
        rfdr=0x4C,              //Receive Filter Data Register
        pmctrl=0xB0,            //Power Management Control Register
        pmer=0xB4               //Power Management Wake-up Event Register
};

/* Symbolic names for bits in various registers */
enum sis900_command_register_bits {
	RELOAD  = 0x00000400, ACCESSMODE = 0x00000200,/* ET */
	RESET   = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020,
	TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004,
	TxDIS   = 0x00000002, TxENA = 0x00000001
};

enum sis900_configuration_register_bits {
	DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
	SB    = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
	PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
	/* 635 & 900B Specific */
	RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
	EDB_MASTER_EN = 0x00002000
};

enum sis900_eeprom_access_register_bits {
	MDC  = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
	EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
	EEDI = 0x00000001
};

enum sis900_interrupt_register_bits {
	WKEVT  = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000,
	TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000,
	SSERR  = 0x00400000, RMABT  = 0x00200000, RTABT = 0x00100000,
	RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000,
	MIBINT = 0x00000800, TxURN  = 0x00000400, TxIDLE  = 0x00000200,
	TxERR  = 0x00000100, TxDESC = 0x00000080, TxOK  = 0x00000040,
	RxORN  = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008,
	RxERR  = 0x00000004, RxDESC = 0x00000002, RxOK  = 0x00000001
};

enum sis900_interrupt_enable_register_bits {
	IE = 0x00000001
};

/* maximum dma burst for transmission and receive */
#define MAX_DMA_RANGE	7	/* actually 0 means MAXIMUM !! */
#define TxMXDMA_shift   	20
#define RxMXDMA_shift    20

enum sis900_tx_rx_dma{
	DMA_BURST_512 = 0,	DMA_BURST_64 = 5
};

/* transmit FIFO thresholds */
#define TX_FILL_THRESH   16	/* 1/4 FIFO size */
#define TxFILLT_shift   	8
#define TxDRNT_shift    	0
#define TxDRNT_100      	48	/* 3/4 FIFO size */
#define TxDRNT_10		16 	/* 1/2 FIFO size */

enum sis900_transmit_config_register_bits {
	TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000,
	TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00,
	TxDRNT = 0x0000003F
};

/* recevie FIFO thresholds */
#define RxDRNT_shift     1
#define RxDRNT_100	16	/* 1/2 FIFO size */
#define RxDRNT_10		24 	/* 3/4 FIFO size */

enum sis900_reveive_config_register_bits {

Annotation

Detected declarations: `enum sis900_registers`, `enum sis900_command_register_bits`, `enum sis900_configuration_register_bits`, `enum sis900_eeprom_access_register_bits`, `enum sis900_interrupt_register_bits`, `enum sis900_interrupt_enable_register_bits`, `enum sis900_tx_rx_dma`, `enum sis900_transmit_config_register_bits`, `enum sis900_reveive_config_register_bits`, `enum sis900_receive_filter_control_register_bits`.
Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.