drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c- Extension
.c- Size
- 19399 bytes
- Lines
- 693
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mfd/altera-sysmgr.hlinux/clocksource_ids.hlinux/of.hlinux/of_address.hlinux/of_net.hlinux/phy.hlinux/regmap.hlinux/mdio/mdio-regmap.hlinux/pcs-lynx.hlinux/reset.hlinux/stmmac.hdwxgmac2.hstmmac.hstmmac_platform.hstmmac_ptp.h
Detected Declarations
struct socfpga_dwmacstruct socfpga_dwmac_opsstruct socfpga_dwmacfunction socfpga_get_plat_phymodefunction socfpga_sgmii_configfunction socfpga_dwmac_fix_mac_speedfunction socfpga_dwmac_parse_datafunction socfpga_set_phy_mode_commonfunction get_smtgtimefunction smtg_crosststampfunction socfpga_gen5_set_phy_modefunction socfpga_gen10_set_phy_modefunction socfpga_dwmac_pcs_initfunction socfpga_dwmac_pcs_exitfunction socfpga_dwmac_initfunction socfpga_gen5_setup_plat_datfunction socfpga_agilex5_setup_plat_datfunction socfpga_dwmac_probe
Annotated Snippet
struct socfpga_dwmac_ops {
int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv,
struct device *dev);
void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
};
struct socfpga_dwmac {
u32 reg_offset;
u32 reg_shift;
struct plat_stmmacenet_data *plat_dat;
struct regmap *sys_mgr_base_addr;
struct reset_control *stmmac_rst;
struct reset_control *stmmac_ocp_rst;
void __iomem *splitter_base;
void __iomem *tse_pcs_base;
void __iomem *sgmii_adapter_base;
bool f2h_ptp_ref_clk;
const struct socfpga_dwmac_ops *ops;
};
static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
{
return dwmac->plat_dat->phy_interface;
}
static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
{
u16 val = enable ? SGMII_ADAPTER_ENABLE : SGMII_ADAPTER_DISABLE;
writew(val, dwmac->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
}
static void socfpga_dwmac_fix_mac_speed(void *bsp_priv,
phy_interface_t interface, int speed,
unsigned int mode)
{
struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)bsp_priv;
void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base;
phy_interface_t phymode = socfpga_get_plat_phymode(dwmac);
void __iomem *splitter_base = dwmac->splitter_base;
u32 val;
if (sgmii_adapter_base)
socfpga_sgmii_config(dwmac, false);
if (splitter_base) {
val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
switch (speed) {
case 1000:
val |= EMAC_SPLITTER_CTRL_SPEED_1000;
break;
case 100:
val |= EMAC_SPLITTER_CTRL_SPEED_100;
break;
case 10:
val |= EMAC_SPLITTER_CTRL_SPEED_10;
break;
default:
return;
}
writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
}
if ((phymode == PHY_INTERFACE_MODE_SGMII ||
phymode == PHY_INTERFACE_MODE_1000BASEX) && sgmii_adapter_base)
socfpga_sgmii_config(dwmac, true);
}
static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
{
struct device_node *np = dev->of_node;
struct regmap *sys_mgr_base_addr;
u32 reg_offset, reg_shift;
int ret, index;
struct device_node *np_splitter = NULL;
struct device_node *np_sgmii_adapter = NULL;
struct resource res_splitter;
struct resource res_tse_pcs;
struct resource res_sgmii_adapter;
sys_mgr_base_addr =
altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
if (IS_ERR(sys_mgr_base_addr)) {
dev_info(dev, "No sysmgr-syscon node found\n");
return PTR_ERR(sys_mgr_base_addr);
}
ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
Annotation
- Immediate include surface: `linux/mfd/altera-sysmgr.h`, `linux/clocksource_ids.h`, `linux/of.h`, `linux/of_address.h`, `linux/of_net.h`, `linux/phy.h`, `linux/regmap.h`, `linux/mdio/mdio-regmap.h`.
- Detected declarations: `struct socfpga_dwmac`, `struct socfpga_dwmac_ops`, `struct socfpga_dwmac`, `function socfpga_get_plat_phymode`, `function socfpga_sgmii_config`, `function socfpga_dwmac_fix_mac_speed`, `function socfpga_dwmac_parse_data`, `function socfpga_set_phy_mode_common`, `function get_smtgtime`, `function smtg_crosststamp`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.