drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c
Extension
.c
Size
4505 bytes
Lines
160
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer
 *
 * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
 *
 * syscon parts taken from dwmac-sun8i.c, which is
 *
 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/stmmac.h>

#include "stmmac.h"
#include "stmmac_platform.h"

#define SYSCON_REG		0x34

/* RMII specific bits */
#define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
/* Generic system control EMAC_CLK bits */
#define SYSCON_ETXDC_MASK		GENMASK(12, 10)
#define SYSCON_ERXDC_MASK		GENMASK(9, 5)
/* EMAC PHY Interface Type */
#define SYSCON_EPIT			BIT(2) /* 1: RGMII, 0: MII */
#define SYSCON_ETCS_MASK		GENMASK(1, 0)
#define SYSCON_ETCS_MII		0x0
#define SYSCON_ETCS_EXT_GMII	0x1
#define SYSCON_ETCS_INT_GMII	0x2

static int sun55i_gmac200_set_syscon(struct device *dev,
				     struct plat_stmmacenet_data *plat)
{
	struct device_node *node = dev->of_node;
	struct regmap *regmap;
	u32 val, reg = 0;
	int ret;

	regmap = syscon_regmap_lookup_by_phandle(node, "syscon");
	if (IS_ERR(regmap))
		return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n");

	if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) {
		if (val % 100)
			return dev_err_probe(dev, -EINVAL,
					     "tx-delay must be a multiple of 100ps\n");
		val /= 100;
		dev_dbg(dev, "set tx-delay to %x\n", val);
		if (!FIELD_FIT(SYSCON_ETXDC_MASK, val))
			return dev_err_probe(dev, -EINVAL,
					     "TX clock delay exceeds maximum (%u00ps > %lu00ps)\n",
					     val, FIELD_MAX(SYSCON_ETXDC_MASK));

		reg |= FIELD_PREP(SYSCON_ETXDC_MASK, val);
	}

	if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) {
		if (val % 100)
			return dev_err_probe(dev, -EINVAL,
					     "rx-delay must be a multiple of 100ps\n");
		val /= 100;
		dev_dbg(dev, "set rx-delay to %x\n", val);
		if (!FIELD_FIT(SYSCON_ERXDC_MASK, val))
			return dev_err_probe(dev, -EINVAL,
					     "RX clock delay exceeds maximum (%u00ps > %lu00ps)\n",
					     val, FIELD_MAX(SYSCON_ERXDC_MASK));

		reg |= FIELD_PREP(SYSCON_ERXDC_MASK, val);
	}

	switch (plat->phy_interface) {
	case PHY_INTERFACE_MODE_MII:
		/* default */
		break;
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
		break;
	case PHY_INTERFACE_MODE_RMII:

Annotation

Implementation Notes