drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
Extension
.c
Size
29637 bytes
Lines
1046
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (mode == STMMAC_LPI_TIMER) {
			/* Return ERANGE if the timer is larger than the
			 * register field.
			 */
			if (et > STMMAC_ET_MAX)
				return -ERANGE;

			/* Set the hardware LPI entry timer */
			writel(et, ioaddr + GMAC4_LPI_ENTRY_TIMER);

			/* Interpret a zero LPI entry timer to mean
			 * immediate entry into LPI mode.
			 */
			if (et)
				value |= LPI_CTRL_STATUS_LPIATE;
		}

		if (en_tx_lpi_clockgating)
			value |= LPI_CTRL_STATUS_LPITCSE;
	}

	mask = LPI_CTRL_STATUS_LPIATE | LPI_CTRL_STATUS_LPIEN |
	       LPI_CTRL_STATUS_LPITXA | LPI_CTRL_STATUS_LPITCSE;

	value |= readl(ioaddr + GMAC4_LPI_CTRL_STATUS) & ~mask;
	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);

	return 0;
}

static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);

	if (link)
		value |= LPI_CTRL_STATUS_PLS;
	else
		value &= ~LPI_CTRL_STATUS_PLS;

	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
{
	void __iomem *ioaddr = hw->pcsr;
	int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);

	/* Program the timers in the LPI timer control register:
	 * LS: minimum time (ms) for which the link
	 *  status from PHY should be ok before transmitting
	 *  the LPI pattern.
	 * TW: minimum time (us) for which the core waits
	 *  after it has stopped transmitting the LPI pattern.
	 */
	writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
}

static void dwmac4_set_filter(struct mac_device_info *hw,
			      struct net_device *dev)
{
	void __iomem *ioaddr = (void __iomem *)dev->base_addr;
	int numhashregs = (hw->multicast_filter_bins >> 5);
	int mcbitslog2 = hw->mcast_bits_log2;
	unsigned int value;
	u32 mc_filter[8];
	int i;

	memset(mc_filter, 0, sizeof(mc_filter));

	value = readl(ioaddr + GMAC_PACKET_FILTER);
	value &= ~GMAC_PACKET_FILTER_HMC;
	value &= ~GMAC_PACKET_FILTER_HPF;
	value &= ~GMAC_PACKET_FILTER_PCF;
	value &= ~GMAC_PACKET_FILTER_PM;
	value &= ~GMAC_PACKET_FILTER_PR;
	value &= ~GMAC_PACKET_FILTER_RA;
	if (dev->flags & IFF_PROMISC) {
		/* VLAN Tag Filter Fail Packets Queuing */
		if (hw->vlan_fail_q_en) {
			value = readl(ioaddr + GMAC_RXQ_CTRL4);
			value &= ~GMAC_RXQCTRL_VFFQ_MASK;
			value |= GMAC_RXQCTRL_VFFQE |
				 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
			writel(value, ioaddr + GMAC_RXQ_CTRL4);
			value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
		} else {
			value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;

Annotation

Implementation Notes