drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
Extension
.h
Size
7170 bytes
Lines
201
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DWMAC4_DMA_H__
#define __DWMAC4_DMA_H__

/* Define the max channel number used for tx (also rx).
 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
 */
#define DMA_CHANNEL_NB_MAX		1

#define DMA_BUS_MODE			0x00001000

#define DMA_BUS_MODE_DCHE		BIT(19)
#define DMA_BUS_MODE_INTM_MASK		GENMASK(17, 16)
#define DMA_BUS_MODE_INTM_MODE1		0x1
#define DMA_BUS_MODE_SFT_RESET		BIT(0)

#define DMA_SYS_BUS_MODE		0x00001004

#define DMA_BUS_MODE_MB			BIT(14)
#define DMA_BUS_MODE_FB			BIT(0)

#define DMA_STATUS			0x00001008

#define DMA_AXI_BUS_MODE		0x00001028

#define DMA_AXI_EN_LPI			BIT(31)
#define DMA_AXI_LPI_XIT_FRM		BIT(30)
#define DMA_AXI_WR_OSR_LMT		GENMASK(27, 24)
#define DMA_AXI_RD_OSR_LMT		GENMASK(19, 16)

#define DMA_SYS_BUS_MB			BIT(14)
#define DMA_SYS_BUS_AAL			DMA_AXI_AAL
#define DMA_SYS_BUS_EAME		BIT(11)
#define DMA_SYS_BUS_FB			BIT(0)

#define DMA_TBS_CTRL			0x00001050

#define DMA_TBS_FTOS			GENMASK(31, 8)
#define DMA_TBS_FTOV			BIT(0)
#define DMA_TBS_DEF_FTOS		(DMA_TBS_FTOS | DMA_TBS_FTOV)

/* Following DMA defines are channel-oriented */
#define DMA_CHAN_BASE_ADDR		0x00001100
#define DMA_CHAN_BASE_OFFSET		0x80

static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
				      const u32 x)
{
	u32 addr;

	if (addrs)
		addr = addrs->dma_chan + (x * addrs->dma_chan_offset);
	else
		addr = DMA_CHAN_BASE_ADDR + (x * DMA_CHAN_BASE_OFFSET);

	return addr;
}

#define DMA_CHAN_CONTROL(addrs, x)	dma_chanx_base_addr(addrs, x)

#define DMA_CHAN_CTRL_PBLX8		BIT(16)
#define DMA_CONTROL_SPH			BIT(24)

#define DMA_CHAN_TX_CONTROL(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x4)

#define DMA_CONTROL_EDSE		BIT(28)
#define DMA_CHAN_TX_CTRL_TXPBL_MASK	GENMASK(21, 16)
#define DMA_CONTROL_TSE			BIT(12)
#define DMA_CONTROL_OSP			BIT(4)
#define DMA_CONTROL_ST			BIT(0)

#define DMA_CHAN_RX_CONTROL(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x8)

#define DMA_CHAN_RX_CTRL_RXPBL_MASK	GENMASK(21, 16)
#define DMA_RBSZ_MASK			GENMASK(14, 1)
#define DMA_CONTROL_SR			BIT(0)

#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x10)
#define DMA_CHAN_TX_BASE_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x14)
#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x18)
#define DMA_CHAN_RX_BASE_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x1c)
#define DMA_CHAN_TX_END_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x20)
#define DMA_CHAN_RX_END_ADDR(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x28)
#define DMA_CHAN_TX_RING_LEN(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x2c)
#define DMA_CHAN_RX_RING_LEN(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x30)

#define DMA_CHAN_INTR_ENA(addrs, x)	(dma_chanx_base_addr(addrs, x) + 0x34)

#define DMA_CHAN_INTR_ENA_NIE		BIT(16)
#define DMA_CHAN_INTR_ENA_AIE		BIT(15)
#define DMA_CHAN_INTR_ENA_NIE_4_10	BIT(15)

Annotation

Implementation Notes