drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c- Extension
.c- Size
- 44158 bytes
- Lines
- 1598
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitrev.hlinux/crc32.hlinux/iopoll.hstmmac.hstmmac_fpe.hstmmac_ptp.hstmmac_vlan.hdwxlgmac2.hdwxgmac2.h
Detected Declarations
struct dwxgmac3_error_descfunction Copyrightfunction dwxgmac2_irq_modifyfunction dwxgmac2_update_capsfunction dwxgmac2_set_macfunction dwxgmac2_rx_ipcfunction dwxgmac2_rx_queue_enablefunction dwxgmac2_rx_queue_priofunction dwxgmac2_tx_queue_priofunction dwxgmac2_rx_queue_routingfunction dwxgmac2_prog_mtl_rx_algorithmsfunction dwxgmac2_prog_mtl_tx_algorithmsfunction dwxgmac2_set_mtl_tx_queue_weightfunction dwxgmac2_map_mtl_to_dmafunction dwxgmac2_config_cbsfunction dwxgmac2_dump_regsfunction dwxgmac2_host_irq_statusfunction dwxgmac2_host_mtl_irq_statusfunction dwxgmac2_flow_ctrlfunction dwxgmac2_pmtfunction dwxgmac2_set_umac_addrfunction dwxgmac2_get_umac_addrfunction dwxgmac2_set_lpi_modefunction dwxgmac2_set_eee_plsfunction dwxgmac2_set_eee_timerfunction dwxgmac2_set_mchashfunction dwxgmac2_set_filterfunction netdev_for_each_mc_addrfunction netdev_for_each_uc_addrfunction dwxgmac2_set_mac_loopbackfunction dwxgmac2_rss_write_regfunction dwxgmac2_rss_configurefunction dwxgmac3_log_errorfunction dwxgmac3_handle_mac_errfunction dwxgmac3_handle_mtl_errfunction dwxgmac3_handle_dma_errfunction dwxgmac3_safety_feat_configfunction dwxgmac3_safety_feat_irq_statusfunction dwxgmac3_safety_feat_dumpfunction dwxgmac3_rxp_disablefunction dwxgmac3_rxp_enablefunction dwxgmac3_rxp_update_single_entryfunction dwxgmac3_rxp_get_next_entryfunction dwxgmac3_rxp_configfunction dwxgmac2_get_mac_tx_timestampfunction dwxgmac2_flex_pps_configfunction dwxgmac2_sarc_configurefunction dwxgmac2_filter_wait
Annotated Snippet
struct dwxgmac3_error_desc {
bool valid;
const char *desc;
const char *detailed_desc;
};
#define STAT_OFF(field) offsetof(struct stmmac_safety_stats, field)
static void dwxgmac3_log_error(struct net_device *ndev, u32 value, bool corr,
const char *module_name,
const struct dwxgmac3_error_desc *desc,
unsigned long field_offset,
struct stmmac_safety_stats *stats)
{
unsigned long loc, mask;
u8 *bptr = (u8 *)stats;
unsigned long *ptr;
ptr = (unsigned long *)(bptr + field_offset);
mask = value;
for_each_set_bit(loc, &mask, 32) {
netdev_err(ndev, "Found %s error in %s: '%s: %s'\n", corr ?
"correctable" : "uncorrectable", module_name,
desc[loc].desc, desc[loc].detailed_desc);
/* Update counters */
ptr[loc]++;
}
}
static const struct dwxgmac3_error_desc dwxgmac3_mac_errors[32]= {
{ true, "ATPES", "Application Transmit Interface Parity Check Error" },
{ true, "DPES", "Descriptor Cache Data Path Parity Check Error" },
{ true, "TPES", "TSO Data Path Parity Check Error" },
{ true, "TSOPES", "TSO Header Data Path Parity Check Error" },
{ true, "MTPES", "MTL Data Path Parity Check Error" },
{ true, "MTSPES", "MTL TX Status Data Path Parity Check Error" },
{ true, "MTBUPES", "MAC TBU Data Path Parity Check Error" },
{ true, "MTFCPES", "MAC TFC Data Path Parity Check Error" },
{ true, "ARPES", "Application Receive Interface Data Path Parity Check Error" },
{ true, "MRWCPES", "MTL RWC Data Path Parity Check Error" },
{ true, "MRRCPES", "MTL RCC Data Path Parity Check Error" },
{ true, "CWPES", "CSR Write Data Path Parity Check Error" },
{ true, "ASRPES", "AXI Slave Read Data Path Parity Check Error" },
{ true, "TTES", "TX FSM Timeout Error" },
{ true, "RTES", "RX FSM Timeout Error" },
{ true, "CTES", "CSR FSM Timeout Error" },
{ true, "ATES", "APP FSM Timeout Error" },
{ true, "PTES", "PTP FSM Timeout Error" },
{ false, "UNKNOWN", "Unknown Error" }, /* 18 */
{ false, "UNKNOWN", "Unknown Error" }, /* 19 */
{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
{ true, "MSTTES", "Master Read/Write Timeout Error" },
{ true, "SLVTES", "Slave Read/Write Timeout Error" },
{ true, "ATITES", "Application Timeout on ATI Interface Error" },
{ true, "ARITES", "Application Timeout on ARI Interface Error" },
{ true, "FSMPES", "FSM State Parity Error" },
{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
{ true, "CPI", "Control Register Parity Check Error" },
};
static void dwxgmac3_handle_mac_err(struct net_device *ndev,
void __iomem *ioaddr, bool correctable,
struct stmmac_safety_stats *stats)
{
u32 value;
value = readl(ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
writel(value, ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
dwxgmac3_log_error(ndev, value, correctable, "MAC",
dwxgmac3_mac_errors, STAT_OFF(mac_errors), stats);
}
static const struct dwxgmac3_error_desc dwxgmac3_mtl_errors[32]= {
{ true, "TXCES", "MTL TX Memory Error" },
{ true, "TXAMS", "MTL TX Memory Address Mismatch Error" },
{ true, "TXUES", "MTL TX Memory Error" },
{ false, "UNKNOWN", "Unknown Error" }, /* 3 */
{ true, "RXCES", "MTL RX Memory Error" },
{ true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
{ true, "RXUES", "MTL RX Memory Error" },
{ false, "UNKNOWN", "Unknown Error" }, /* 7 */
{ true, "ECES", "MTL EST Memory Error" },
{ true, "EAMS", "MTL EST Memory Address Mismatch Error" },
Annotation
- Immediate include surface: `linux/bitrev.h`, `linux/crc32.h`, `linux/iopoll.h`, `stmmac.h`, `stmmac_fpe.h`, `stmmac_ptp.h`, `stmmac_vlan.h`, `dwxlgmac2.h`.
- Detected declarations: `struct dwxgmac3_error_desc`, `function Copyright`, `function dwxgmac2_irq_modify`, `function dwxgmac2_update_caps`, `function dwxgmac2_set_mac`, `function dwxgmac2_rx_ipc`, `function dwxgmac2_rx_queue_enable`, `function dwxgmac2_rx_queue_prio`, `function dwxgmac2_tx_queue_prio`, `function dwxgmac2_rx_queue_routing`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.