drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
Extension
.c
Size
18204 bytes
Lines
614
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (fifosz) {
		case 4096:
			/* This violates the above formula because of FIFO size
			 * limit therefore overflow may occur in spite of this.
			 */
			rfd = 0x03; /* Full-2.5K */
			rfa = 0x01; /* Full-1.5K */
			break;

		default:
			rfd = 0x07; /* Full-4.5K */
			rfa = 0x04; /* Full-3K */
			break;
		}

		flow = u32_replace_bits(flow, rfd, XGMAC_RFD);
		flow = u32_replace_bits(flow, rfa, XGMAC_RFA);

		writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
	}

	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
}

static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *ioaddr,
				 int mode, u32 channel, int fifosz, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	unsigned int tqs = fifosz / 256 - 1;
	unsigned int ttc, txqen;

	if (mode == SF_DMA_MODE) {
		value |= XGMAC_TSF;
	} else {
		value &= ~XGMAC_TSF;

		if (mode <= 64)
			ttc = 0x0;
		else if (mode <= 96)
			ttc = 0x2;
		else if (mode <= 128)
			ttc = 0x3;
		else if (mode <= 192)
			ttc = 0x4;
		else if (mode <= 256)
			ttc = 0x5;
		else if (mode <= 384)
			ttc = 0x6;
		else
			ttc = 0x7;

		value = u32_replace_bits(value, ttc, XGMAC_TTC);
	}

	/* Use static TC to Queue mapping */
	value |= FIELD_PREP(XGMAC_Q2TCMAP, channel);

	if (qmode != MTL_QUEUE_AVB)
		txqen = 0x2;
	else
		txqen = 0x1;

	value = u32_replace_bits(value, txqen, XGMAC_TXQEN);
	value = u32_replace_bits(value, tqs, XGMAC_TQS);

	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
}

static void dwxgmac2_enable_dma_irq(struct stmmac_priv *priv,
				    void __iomem *ioaddr, u32 chan,
				    bool rx, bool tx)
{
	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));

	if (rx)
		value |= XGMAC_DMA_INT_DEFAULT_RX;
	if (tx)
		value |= XGMAC_DMA_INT_DEFAULT_TX;

	writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_disable_dma_irq(struct stmmac_priv *priv,
				     void __iomem *ioaddr, u32 chan,
				     bool rx, bool tx)
{
	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));

	if (rx)
		value &= ~XGMAC_DMA_INT_DEFAULT_RX;

Annotation

Implementation Notes