drivers/net/ethernet/sun/niu.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/sun/niu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/sun/niu.c- Extension
.c- Size
- 236129 bytes
- Lines
- 10268
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/init.hlinux/interrupt.hlinux/pci.hlinux/dma-mapping.hlinux/netdevice.hlinux/ethtool.hlinux/etherdevice.hlinux/platform_device.hlinux/delay.hlinux/bitops.hlinux/mii.hlinux/if.hlinux/if_ether.hlinux/if_vlan.hlinux/ip.hlinux/in.hlinux/ipv6.hlinux/log2.hlinux/jiffies.hlinux/crc32.hlinux/list.hlinux/slab.hlinux/io.hlinux/of.hniu.h
Detected Declarations
struct niu_phy_templatefunction readqfunction writeqfunction __niu_wait_bits_clear_macfunction __niu_set_and_wait_clear_macfunction __niu_wait_bits_clear_ippfunction __niu_set_and_wait_clear_ippfunction __niu_wait_bits_clearfunction __niu_set_and_wait_clearfunction niu_ldg_rearmfunction niu_ldn_irq_enablefunction niu_enable_ldn_in_ldgfunction niu_enable_interruptsfunction phy_encodefunction phy_decodefunction mdio_waitfunction mdio_readfunction mdio_writefunction mii_readfunction mii_writefunction esr2_set_tx_cfgfunction esr2_set_rx_cfgfunction serdes_init_niu_10g_fiberfunction serdes_init_niu_1g_serdesfunction serdes_init_niu_10g_serdesfunction esr_read_rxtx_ctrlfunction esr_read_glue0function esr_read_resetfunction esr_write_rxtx_ctrlfunction esr_write_glue0function esr_resetfunction serdes_init_10gfunction serdes_init_1gfunction serdes_init_1g_serdesfunction link_status_1g_serdesfunction link_status_10g_serdesfunction link_status_miifunction link_status_1g_rgmiifunction link_status_1gfunction bcm8704_resetfunction bcm8704_user_dev3_readbackfunction bcm8706_init_user_dev3function bcm8704_init_user_dev3function mrvl88x2011_act_ledfunction mrvl88x2011_led_blink_ratefunction xcvr_init_10g_mrvl88x2011function xcvr_diag_bcm870xfunction xcvr_10g_set_lb_bcm870x
Annotated Snippet
static const struct net_device_ops niu_netdev_ops = {
.ndo_open = niu_open,
.ndo_stop = niu_close,
.ndo_start_xmit = niu_start_xmit,
.ndo_get_stats64 = niu_get_stats,
.ndo_set_rx_mode = niu_set_rx_mode,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = niu_set_mac_addr,
.ndo_eth_ioctl = niu_ioctl,
.ndo_tx_timeout = niu_tx_timeout,
.ndo_change_mtu = niu_change_mtu,
};
static void niu_assign_netdev_ops(struct net_device *dev)
{
dev->netdev_ops = &niu_netdev_ops;
dev->ethtool_ops = &niu_ethtool_ops;
dev->watchdog_timeo = NIU_TX_TIMEOUT;
}
static void niu_device_announce(struct niu *np)
{
struct net_device *dev = np->dev;
pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
dev->name,
(np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
(np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
(np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
(np->mac_xcvr == MAC_XCVR_MII ? "MII" :
(np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
np->vpd.phy_type);
} else {
pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
dev->name,
(np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
(np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
(np->flags & NIU_FLAGS_FIBER ? "FIBER" :
(np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
"COPPER")),
(np->mac_xcvr == MAC_XCVR_MII ? "MII" :
(np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
np->vpd.phy_type);
}
}
static void niu_set_basic_features(struct net_device *dev)
{
dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
dev->features |= dev->hw_features | NETIF_F_RXCSUM;
}
static int niu_pci_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
union niu_parent_id parent_id;
struct net_device *dev;
struct niu *np;
int err;
niu_driver_version();
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
return err;
}
if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
err = -ENODEV;
goto err_out_disable_pdev;
}
err = pci_request_regions(pdev, DRV_MODULE_NAME);
if (err) {
dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
goto err_out_disable_pdev;
}
if (!pci_is_pcie(pdev)) {
dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
err = -ENODEV;
goto err_out_free_res;
}
Annotation
- Immediate include surface: `linux/module.h`, `linux/init.h`, `linux/interrupt.h`, `linux/pci.h`, `linux/dma-mapping.h`, `linux/netdevice.h`, `linux/ethtool.h`, `linux/etherdevice.h`.
- Detected declarations: `struct niu_phy_template`, `function readq`, `function writeq`, `function __niu_wait_bits_clear_mac`, `function __niu_set_and_wait_clear_mac`, `function __niu_wait_bits_clear_ipp`, `function __niu_set_and_wait_clear_ipp`, `function __niu_wait_bits_clear`, `function __niu_set_and_wait_clear`, `function niu_ldg_rearm`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.