drivers/net/ethernet/sun/niu.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/sun/niu.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/sun/niu.h
Extension: .h
Size: 122864 bytes
Lines: 3312
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Touches IRQ or DMA behavior; this matters for the representative real-device path.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

struct fcram_hash_opt
struct fcram_hash_ipv4
struct fcram_hash_ipv6
struct rx_pkt_hdr0
struct rx_pkt_hdr1
struct tx_dma_mbox
struct tx_pkt_hdr
struct tx_buff_info
struct txdma_mailbox
struct tx_ring_info
struct rxdma_mailbox
struct rx_ring_info
struct niu_vpd
struct niu_altmac_rdc
struct niu_vlan_rdc
struct niu_classifier
struct rdc_table
struct niu_rdc_tables
struct phy_probe_info
struct niu_tcam_entry
struct device_node
struct niu
struct niu_parent
struct niu_ops
struct niu_link_config
struct niu_ldg
struct niu_xmac_stats
struct niu_bmac_stats
struct niu_phy_ops
struct platform_device
struct niu
function niu_tx_avail

Annotated Snippet

struct fcram_hash_opt {
	u64	header;
};

/* EXT=1, FMT=0 */
struct fcram_hash_ipv4 {
	u64	header;
	u64	addrs;
	u64	ports;
	u64	action;
};

/* EXT=1, FMT=1 */
struct fcram_hash_ipv6 {
	u64	header;
	u64	addrs[4];
	u64	ports;
	u64	action;
};

#define HASH_TBL_DATA_LOG(IDX)		(FFLP + 0x00010UL + (IDX) * 8192UL)
#define  HASH_TBL_DATA_LOG_ERR		0x0000000080000000ULL
#define  HASH_TBL_DATA_LOG_ADDR		0x000000007fffff00ULL
#define  HASH_TBL_DATA_LOG_SYNDROME	0x00000000000000ffULL

#define RX_DMA_CK_DIV			(FZC_DMC + 0x00000UL)
#define  RX_DMA_CK_DIV_CNT		0x000000000000ffffULL

#define DEF_RDC(IDX)			(FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
#define  DEF_RDC_VAL			0x000000000000001fULL

#define PT_DRR_WT(IDX)			(FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
#define  PT_DRR_WT_VAL			0x000000000000ffffULL

#define PT_DRR_WEIGHT_DEFAULT_10G	0x0400
#define PT_DRR_WEIGHT_DEFAULT_1G	0x0066

#define PT_USE(IDX)			(FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
#define  PT_USE_CNT			0x00000000000fffffULL

#define RED_RAN_INIT			(FZC_DMC + 0x00068UL)
#define  RED_RAN_INIT_OPMODE		0x0000000000010000ULL
#define  RED_RAN_INIT_VAL		0x000000000000ffffULL

#define RX_ADDR_MD			(FZC_DMC + 0x00070UL)
#define  RX_ADDR_MD_DBG_PT_MUX_SEL	0x000000000000000cULL
#define  RX_ADDR_MD_RAM_ACC		0x0000000000000002ULL
#define  RX_ADDR_MD_MODE32		0x0000000000000001ULL

#define RDMC_PRE_PAR_ERR		(FZC_DMC + 0x00078UL)
#define  RDMC_PRE_PAR_ERR_ERR		0x0000000000008000ULL
#define  RDMC_PRE_PAR_ERR_MERR		0x0000000000004000ULL
#define  RDMC_PRE_PAR_ERR_ADDR		0x00000000000000ffULL

#define RDMC_SHA_PAR_ERR		(FZC_DMC + 0x00080UL)
#define  RDMC_SHA_PAR_ERR_ERR		0x0000000000008000ULL
#define  RDMC_SHA_PAR_ERR_MERR		0x0000000000004000ULL
#define  RDMC_SHA_PAR_ERR_ADDR		0x00000000000000ffULL

#define RDMC_MEM_ADDR			(FZC_DMC + 0x00088UL)
#define  RDMC_MEM_ADDR_PRE_SHAD		0x0000000000000100ULL
#define  RDMC_MEM_ADDR_ADDR		0x00000000000000ffULL

#define RDMC_MEM_DAT0			(FZC_DMC + 0x00090UL)
#define  RDMC_MEM_DAT0_DATA		0x00000000ffffffffULL /* bits 31:0 */

#define RDMC_MEM_DAT1			(FZC_DMC + 0x00098UL)
#define  RDMC_MEM_DAT1_DATA		0x00000000ffffffffULL /* bits 63:32 */

#define RDMC_MEM_DAT2			(FZC_DMC + 0x000a0UL)
#define  RDMC_MEM_DAT2_DATA		0x00000000ffffffffULL /* bits 95:64 */

#define RDMC_MEM_DAT3			(FZC_DMC + 0x000a8UL)
#define  RDMC_MEM_DAT3_DATA		0x00000000ffffffffULL /* bits 127:96 */

#define RDMC_MEM_DAT4			(FZC_DMC + 0x000b0UL)
#define  RDMC_MEM_DAT4_DATA		0x00000000000fffffULL /* bits 147:128 */

#define RX_CTL_DAT_FIFO_STAT			(FZC_DMC + 0x000b8UL)
#define  RX_CTL_DAT_FIFO_STAT_ID_MISMATCH	0x0000000000000100ULL
#define  RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR	0x00000000000000f0ULL
#define  RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR	0x000000000000000fULL

#define RX_CTL_DAT_FIFO_MASK			(FZC_DMC + 0x000c0UL)
#define  RX_CTL_DAT_FIFO_MASK_ID_MISMATCH	0x0000000000000100ULL
#define  RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR	0x00000000000000f0ULL
#define  RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR	0x000000000000000fULL

#define RDMC_TRAINING_VECTOR			(FZC_DMC + 0x000c8UL)
#define  RDMC_TRAINING_VECTOR_TRAINING_VECTOR	0x00000000ffffffffULL

Annotation

Detected declarations: `struct fcram_hash_opt`, `struct fcram_hash_ipv4`, `struct fcram_hash_ipv6`, `struct rx_pkt_hdr0`, `struct rx_pkt_hdr1`, `struct tx_dma_mbox`, `struct tx_pkt_hdr`, `struct tx_buff_info`, `struct txdma_mailbox`, `struct tx_ring_info`.
Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.