drivers/net/ethernet/synopsys/dwc-xlgmac-common.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/synopsys/dwc-xlgmac-common.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/synopsys/dwc-xlgmac-common.c
Extension
.c
Size
20751 bytes
Lines
731
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/kernel.h>
#include <linux/module.h>

#include "dwc-xlgmac.h"
#include "dwc-xlgmac-reg.h"

static int debug = -1;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)");
static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
				      NETIF_MSG_IFUP);

static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7};

static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata)
{
	struct net_device *netdev = pdata->netdev;

	/* Currently it uses a static mac address for test */
	memcpy(pdata->mac_addr, dev_addr, netdev->addr_len);
}

static void xlgmac_default_config(struct xlgmac_pdata *pdata)
{
	pdata->tx_osp_mode = DMA_OSP_ENABLE;
	pdata->tx_sf_mode = MTL_TSF_ENABLE;
	pdata->rx_sf_mode = MTL_RSF_DISABLE;
	pdata->pblx8 = DMA_PBL_X8_ENABLE;
	pdata->tx_pbl = DMA_PBL_32;
	pdata->rx_pbl = DMA_PBL_32;
	pdata->tx_threshold = MTL_TX_THRESHOLD_128;
	pdata->rx_threshold = MTL_RX_THRESHOLD_128;
	pdata->tx_pause = 1;
	pdata->rx_pause = 1;
	pdata->phy_speed = SPEED_25000;
	pdata->sysclk_rate = XLGMAC_SYSCLOCK;

	strscpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name));
	strscpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver));
}

static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata)
{
	xlgmac_init_desc_ops(&pdata->desc_ops);
	xlgmac_init_hw_ops(&pdata->hw_ops);
}

static int xlgmac_init(struct xlgmac_pdata *pdata)
{
	struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops;
	struct net_device *netdev = pdata->netdev;
	unsigned int i;
	int ret;

	/* Set default configuration data */
	xlgmac_default_config(pdata);

	/* Set irq, base_addr, MAC address, */
	netdev->irq = pdata->dev_irq;
	netdev->base_addr = (unsigned long)pdata->mac_regs;
	xlgmac_read_mac_addr(pdata);
	eth_hw_addr_set(netdev, pdata->mac_addr);

	/* Set all the function pointers */
	xlgmac_init_all_ops(pdata);

	/* Issue software reset to device */
	hw_ops->exit(pdata);

	/* Populate the hardware features */
	xlgmac_get_all_hw_features(pdata);
	xlgmac_print_all_hw_features(pdata);

	/* TODO: Set the PHY mode to XLGMII */

	/* Set the DMA mask */
	ret = dma_set_mask_and_coherent(pdata->dev,
					DMA_BIT_MASK(pdata->hw_feat.dma_width));
	if (ret) {
		dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n");
		return ret;
	}

	/* Channel and ring params initializtion
	 *  pdata->channel_count;
	 *  pdata->tx_ring_count;
	 *  pdata->rx_ring_count;
	 *  pdata->tx_desc_count;
	 *  pdata->rx_desc_count;
	 */

Annotation

Implementation Notes