drivers/net/ethernet/tehuti/tn40_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/tehuti/tn40_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/tehuti/tn40_regs.h
Extension
.h
Size
7629 bytes
Lines
246
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _TN40_REGS_H_
#define _TN40_REGS_H_

/* Register region size */
#define TN40_REGS_SIZE 0x10000

/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
#define TN40_REG_TXD_CFG1_0 0x4000
#define TN40_REG_TXD_CFG1_1 0x4004
#define TN40_REG_TXD_CFG1_2 0x4008
#define TN40_REG_TXD_CFG1_3 0x400C

#define TN40_REG_RXF_CFG1_0 0x4010
#define TN40_REG_RXF_CFG1_1 0x4014
#define TN40_REG_RXF_CFG1_2 0x4018
#define TN40_REG_RXF_CFG1_3 0x401C

#define TN40_REG_RXD_CFG1_0 0x4020
#define TN40_REG_RXD_CFG1_1 0x4024
#define TN40_REG_RXD_CFG1_2 0x4028
#define TN40_REG_RXD_CFG1_3 0x402C

#define TN40_REG_TXF_CFG1_0 0x4030
#define TN40_REG_TXF_CFG1_1 0x4034
#define TN40_REG_TXF_CFG1_2 0x4038
#define TN40_REG_TXF_CFG1_3 0x403C

#define TN40_REG_TXD_CFG0_0 0x4040
#define TN40_REG_TXD_CFG0_1 0x4044
#define TN40_REG_TXD_CFG0_2 0x4048
#define TN40_REG_TXD_CFG0_3 0x404C

#define TN40_REG_RXF_CFG0_0 0x4050
#define TN40_REG_RXF_CFG0_1 0x4054
#define TN40_REG_RXF_CFG0_2 0x4058
#define TN40_REG_RXF_CFG0_3 0x405C

#define TN40_REG_RXD_CFG0_0 0x4060
#define TN40_REG_RXD_CFG0_1 0x4064
#define TN40_REG_RXD_CFG0_2 0x4068
#define TN40_REG_RXD_CFG0_3 0x406C

#define TN40_REG_TXF_CFG0_0 0x4070
#define TN40_REG_TXF_CFG0_1 0x4074
#define TN40_REG_TXF_CFG0_2 0x4078
#define TN40_REG_TXF_CFG0_3 0x407C

#define TN40_REG_TXD_WPTR_0 0x4080
#define TN40_REG_TXD_WPTR_1 0x4084
#define TN40_REG_TXD_WPTR_2 0x4088
#define TN40_REG_TXD_WPTR_3 0x408C

#define TN40_REG_RXF_WPTR_0 0x4090
#define TN40_REG_RXF_WPTR_1 0x4094
#define TN40_REG_RXF_WPTR_2 0x4098
#define TN40_REG_RXF_WPTR_3 0x409C

#define TN40_REG_RXD_WPTR_0 0x40A0
#define TN40_REG_RXD_WPTR_1 0x40A4
#define TN40_REG_RXD_WPTR_2 0x40A8
#define TN40_REG_RXD_WPTR_3 0x40AC

#define TN40_REG_TXF_WPTR_0 0x40B0
#define TN40_REG_TXF_WPTR_1 0x40B4
#define TN40_REG_TXF_WPTR_2 0x40B8
#define TN40_REG_TXF_WPTR_3 0x40BC

#define TN40_REG_TXD_RPTR_0 0x40C0
#define TN40_REG_TXD_RPTR_1 0x40C4
#define TN40_REG_TXD_RPTR_2 0x40C8
#define TN40_REG_TXD_RPTR_3 0x40CC

#define TN40_REG_RXF_RPTR_0 0x40D0
#define TN40_REG_RXF_RPTR_1 0x40D4
#define TN40_REG_RXF_RPTR_2 0x40D8
#define TN40_REG_RXF_RPTR_3 0x40DC

#define TN40_REG_RXD_RPTR_0 0x40E0
#define TN40_REG_RXD_RPTR_1 0x40E4
#define TN40_REG_RXD_RPTR_2 0x40E8
#define TN40_REG_RXD_RPTR_3 0x40EC

#define TN40_REG_TXF_RPTR_0 0x40F0
#define TN40_REG_TXF_RPTR_1 0x40F4
#define TN40_REG_TXF_RPTR_2 0x40F8
#define TN40_REG_TXF_RPTR_3 0x40FC

/* Hardware versioning */
#define TN40_FPGA_VER 0x5030

Annotation

Implementation Notes