drivers/net/ethernet/ti/cpsw_sl.c

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/ti/cpsw_sl.c

Extension

.c

Size

8761 bytes

Lines

340

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/delay.h
• linux/io.h
• linux/kernel.h
• cpsw_sl.h

Detected Declarations

• struct cpsw_sl
• struct cpsw_sl_dev_id
• function cpsw_sl_reg_read
• function cpsw_sl_reg_write
• function cpsw_sl_reset
• function cpsw_sl_ctl_set
• function cpsw_sl_ctl_clr
• function cpsw_sl_ctl_reset
• function cpsw_sl_wait_for_idle
• export cpsw_sl_reg_read
• export cpsw_sl_reg_write
• export cpsw_sl_get
• export cpsw_sl_reset
• export cpsw_sl_ctl_set
• export cpsw_sl_ctl_clr
• export cpsw_sl_ctl_reset
• export cpsw_sl_wait_for_idle

Annotated Snippet

struct cpsw_sl {
	struct device *dev;
	void __iomem *sl_base;
	const u16 *regs;
	u32 control_features;
	u32 idle_mask;
};

struct cpsw_sl_dev_id {
	const char *device_id;
	const u16 *regs;
	const u32 control_features;
	const u32 regs_offset;
	const u32 idle_mask;
};

static const struct cpsw_sl_dev_id cpsw_sl_id_match[] = {
	{
		.device_id = "cpsw",
		.regs = cpsw_sl_reg_map_cpsw,
		.control_features = CPSW_SL_CTL_FUNC_BASE |
				    CPSW_SL_CTL_MTEST |
				    CPSW_SL_CTL_TX_SHORT_GAP_EN |
				    CPSW_SL_CTL_TX_SG_LIM_EN,
		.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
	},
	{
		.device_id = "66ak2hk",
		.regs = cpsw_sl_reg_map_66ak2hk,
		.control_features = CPSW_SL_CTL_FUNC_BASE |
				    CPSW_SL_CTL_TX_SHORT_GAP_EN,
		.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
	},
	{
		.device_id = "66ak2x_xgbe",
		.regs = cpsw_sl_reg_map_66ak2x_xgbe,
		.control_features = CPSW_SL_CTL_FUNC_BASE |
				    CPSW_SL_CTL_XGIG |
				    CPSW_SL_CTL_TX_SHORT_GAP_EN |
				    CPSW_SL_CTL_CRC_TYPE |
				    CPSW_SL_CTL_XGMII_EN,
		.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
	},
	{
		.device_id = "66ak2el",
		.regs = cpsw_sl_reg_map_66ak2elg_am65,
		.regs_offset = 0x330,
		.control_features = CPSW_SL_CTL_FUNC_BASE |
				    CPSW_SL_CTL_MTEST |
				    CPSW_SL_CTL_TX_SHORT_GAP_EN |
				    CPSW_SL_CTL_CRC_TYPE |
				    CPSW_SL_CTL_EXT_EN_RX_FLO |
				    CPSW_SL_CTL_EXT_EN_TX_FLO |
				    CPSW_SL_CTL_TX_SG_LIM_EN,
		.idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
	},
	{
		.device_id = "66ak2g",
		.regs = cpsw_sl_reg_map_66ak2elg_am65,
		.regs_offset = 0x330,
		.control_features = CPSW_SL_CTL_FUNC_BASE |
				    CPSW_SL_CTL_MTEST |
				    CPSW_SL_CTL_CRC_TYPE |
				    CPSW_SL_CTL_EXT_EN_RX_FLO |
				    CPSW_SL_CTL_EXT_EN_TX_FLO,
	},
	{
		.device_id = "am65",
		.regs = cpsw_sl_reg_map_66ak2elg_am65,
		.regs_offset = 0x330,
		.control_features = CPSW_SL_CTL_FUNC_BASE |
				    CPSW_SL_CTL_MTEST |
				    CPSW_SL_CTL_XGIG |
				    CPSW_SL_CTL_TX_SHORT_GAP_EN |
				    CPSW_SL_CTL_CRC_TYPE |
				    CPSW_SL_CTL_XGMII_EN |
				    CPSW_SL_CTL_EXT_EN_RX_FLO |
				    CPSW_SL_CTL_EXT_EN_TX_FLO |
				    CPSW_SL_CTL_TX_SG_LIM_EN |
				    CPSW_SL_CTL_EXT_EN_XGIG,
		.idle_mask = CPSW_SL_STATUS_IDLE_MASK_K3,
	},
	{ },
};

u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg)
{
	int val;

	if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) {

Annotation

• Immediate include surface: `linux/delay.h`, `linux/io.h`, `linux/kernel.h`, `cpsw_sl.h`.
• Detected declarations: `struct cpsw_sl`, `struct cpsw_sl_dev_id`, `function cpsw_sl_reg_read`, `function cpsw_sl_reg_write`, `function cpsw_sl_reset`, `function cpsw_sl_ctl_set`, `function cpsw_sl_ctl_clr`, `function cpsw_sl_ctl_reset`, `function cpsw_sl_wait_for_idle`, `export cpsw_sl_reg_read`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: integration implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.