drivers/net/ethernet/ti/icssg/icssg_config.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/ti/icssg/icssg_config.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/ti/icssg/icssg_config.h
Extension
.h
Size
10581 bytes
Lines
336
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct icssg_buffer_pool_cfg {
	__le32	addr;
	__le32	len;
} __packed;

struct icssg_flow_cfg {
	__le16 rx_base_flow;
	__le16 mgm_base_flow;
} __packed;

#define PRUETH_PKT_TYPE_CMD	0x10
#define PRUETH_NAV_PS_DATA_SIZE	16	/* Protocol specific data size */
#define PRUETH_NAV_SW_DATA_SIZE	16	/* SW related data size */
#define PRUETH_MAX_TX_DESC	512
#define PRUETH_MAX_RX_DESC	512
#define PRUETH_MAX_RX_FLOWS	1	/* excluding default flow */
#define PRUETH_RX_FLOW_DATA	0

/* Defines for forwarding path buffer pools:
 *   - used by firmware to store packets to be forwarded to other port
 *   - 8 total pools per slice
 *   - only used in switch mode (as no forwarding in mac mode)
 */
#define PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE			8
#define PRUETH_SW_FWD_BUF_POOL_SIZE				(SZ_8K)

/* Defines for local injection path buffer pools:
 *   - used by firmware to store packets received from host core
 *   - 16 total pools per slice
 *   - 8 pools per port per slice and each slice handles both ports
 *   - only 4 out of 8 pools used per port (as only 4 real QoS levels in ICSSG)
 *   - switch mode: 8 total pools used
 *   - mac mode:    4 total pools used
 */
#define PRUETH_NUM_LI_BUF_POOLS_PER_SLICE			16
#define PRUETH_NUM_LI_BUF_POOLS_PER_PORT_PER_SLICE		8
#define PRUETH_SW_LI_BUF_POOL_SIZE				SZ_4K
#define PRUETH_SW_USED_LI_BUF_POOLS_PER_SLICE			8
#define PRUETH_SW_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE		4
#define PRUETH_EMAC_LI_BUF_POOL_SIZE				SZ_8K
#define PRUETH_EMAC_USED_LI_BUF_POOLS_PER_SLICE			4
#define PRUETH_EMAC_USED_LI_BUF_POOLS_PER_PORT_PER_SLICE	4

/* Defines for host egress path - express and preemptible buffers
 *   - used by firmware to store express and preemptible packets
 *     to be transmitted to host core
 *   - used by both mac/switch modes
 */
#define PRUETH_SW_HOST_EXP_BUF_POOL_SIZE	SZ_16K
#define PRUETH_SW_HOST_PRE_BUF_POOL_SIZE	(SZ_16K - SZ_2K)
#define PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE	PRUETH_SW_HOST_EXP_BUF_POOL_SIZE
#define PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE	PRUETH_SW_HOST_PRE_BUF_POOL_SIZE

/* Buffer used by firmware to temporarily store packet to be dropped */
#define PRUETH_SW_DROP_PKT_BUF_SIZE		SZ_2K
#define PRUETH_EMAC_DROP_PKT_BUF_SIZE		PRUETH_SW_DROP_PKT_BUF_SIZE

/* Total switch mode memory usage for buffers per slice */
#define PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE \
	(PRUETH_SW_FWD_BUF_POOL_SIZE * PRUETH_NUM_FWD_BUF_POOLS_PER_SLICE + \
	 PRUETH_SW_LI_BUF_POOL_SIZE * PRUETH_SW_USED_LI_BUF_POOLS_PER_SLICE + \
	 PRUETH_SW_HOST_EXP_BUF_POOL_SIZE + \
	 PRUETH_SW_HOST_PRE_BUF_POOL_SIZE + \
	 PRUETH_SW_DROP_PKT_BUF_SIZE)

/* Total switch mode memory usage for all buffers */
#define PRUETH_SW_TOTAL_BUF_SIZE \
	(2 * PRUETH_SW_TOTAL_BUF_SIZE_PER_SLICE)

/* Total mac mode memory usage for buffers per slice */
#define PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE \
	(PRUETH_EMAC_LI_BUF_POOL_SIZE * \
	 PRUETH_EMAC_USED_LI_BUF_POOLS_PER_SLICE + \
	 PRUETH_EMAC_HOST_EXP_BUF_POOL_SIZE + \
	 PRUETH_EMAC_HOST_PRE_BUF_POOL_SIZE + \
	 PRUETH_EMAC_DROP_PKT_BUF_SIZE)

/* Total mac mode memory usage for all buffers */
#define PRUETH_EMAC_TOTAL_BUF_SIZE \
	(2 * PRUETH_EMAC_TOTAL_BUF_SIZE_PER_SLICE)

/* Size of 1 bank of MSMC/OC_SRAM memory */
#define MSMC_RAM_BANK_SIZE			SZ_256K

#define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1)

struct icssg_rxq_ctx {
	__le32 start[3];
	__le32 end;
} __packed;

Annotation

Implementation Notes