drivers/net/ethernet/ti/icssg/icssg_switch_map.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/ti/icssg/icssg_switch_map.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/ti/icssg/icssg_switch_map.h
Extension
.h
Size
10064 bytes
Lines
271
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __NET_TI_ICSSG_SWITCH_MAP_H
#define __NET_TI_ICSSG_SWITCH_MAP_H

/************************* Ethernet Switch Constants *********************/

/* if bucket size is changed in firmware then this too should be changed
 * because it directly impacts FDB ageing calculation
 */
#define NUMBER_OF_FDB_BUCKET_ENTRIES            (4)

/* This is fixed in ICSSG */
#define SIZE_OF_FDB                             (2048)

#define FW_LINK_SPEED_1G                           (0x00)
#define FW_LINK_SPEED_100M                         (0x01)
#define FW_LINK_SPEED_10M                          (0x02)
#define FW_LINK_SPEED_HD                           (0x80)

/* Time after which FDB entries are checked for aged out values.
 * Values are in nanoseconds
 */
#define FDB_AGEING_TIMEOUT_OFFSET                          0x0014

/* Default VLAN tag for Host Port */
#define HOST_PORT_DF_VLAN_OFFSET                           0x001C

/* Same as HOST_PORT_DF_VLAN_OFFSET */
#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET        HOST_PORT_DF_VLAN_OFFSET

/* Default VLAN tag for P1 Port */
#define P1_PORT_DF_VLAN_OFFSET                             0x0020

/* Same as P1_PORT_DF_VLAN_OFFSET */
#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET        P1_PORT_DF_VLAN_OFFSET

/* default VLAN tag for P2 Port */
#define P2_PORT_DF_VLAN_OFFSET                             0x0024

/* Same as P2_PORT_DF_VLAN_OFFSET */
#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET        P2_PORT_DF_VLAN_OFFSET

/* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */
#define VLAN_STATIC_REG_TABLE_OFFSET                       0x0100

/* VLAN-FID Table offset for EMAC  */
#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET        VLAN_STATIC_REG_TABLE_OFFSET

/* Packet descriptor Q reserved memory */
#define PORT_DESC0_HI                                      0x2104

/* Packet descriptor Q reserved memory */
#define PORT_DESC0_LO                                      0x2F6C

/* Packet descriptor Q reserved memory */
#define PORT_DESC1_HI                                      0x3DD4

/* Packet descriptor Q reserved memory */
#define PORT_DESC1_LO                                      0x4C3C

/* Packet descriptor Q reserved memory */
#define HOST_DESC0_HI                                      0x5AA4

/* Packet descriptor Q reserved memory */
#define HOST_DESC0_LO                                      0x5F0C

/* Packet descriptor Q reserved memory */
#define HOST_DESC1_HI                                      0x6374

/* Packet descriptor Q reserved memory */
#define HOST_DESC1_LO                                      0x67DC

/* Special packet descriptor Q reserved memory */
#define HOST_SPPD0                                         0x7AAC

/* Special acket descriptor Q reserved memory */
#define HOST_SPPD1                                         0x7EAC

/* IEP count cycle counter*/
#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET                   0x83EC

/* IEP count hi roll over count */
#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET            0x83F4

/* IEP count hi sw counter */
#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET           0x83F8

/* Set clock descriptor */
#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET                0x83FC

/* IEP count syncout reduction factor */

Annotation

Implementation Notes