drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
Extension
.h
Size
17357 bytes
Lines
486
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct txgbe_fdir_filter {
	struct hlist_node fdir_node;
	union txgbe_atr_input filter;
	u16 sw_idx;
	u64 action;
};

/* TX/RX descriptor defines */
#define TXGBE_DEFAULT_TXD               512
#define TXGBE_DEFAULT_TX_WORK           256

#if (PAGE_SIZE < 8192)
#define TXGBE_DEFAULT_RXD               512
#define TXGBE_DEFAULT_RX_WORK           256
#else
#define TXGBE_DEFAULT_RXD               256
#define TXGBE_DEFAULT_RX_WORK           128
#endif

#define TXGBE_INTR_MISC(A)    BIT((A)->num_q_vectors)
#define TXGBE_INTR_QALL(A)    (TXGBE_INTR_MISC(A) - 1)

#define TXGBE_MAX_EITR        GENMASK(11, 3)

extern char txgbe_driver_name[];

void txgbe_down(struct wx *wx);
void txgbe_up(struct wx *wx);
int txgbe_setup_tc(struct net_device *dev, u8 tc);
void txgbe_do_reset(struct net_device *netdev);

#define DECLARE_PHY_INTERFACE_MASK_ZERO(name) \
	unsigned long name[PHY_INTERFACE_MODE_MAX] = { 0, }

#define TXGBE_LINK_SPEED_UNKNOWN        0
#define TXGBE_LINK_SPEED_10GB_FULL      4
#define TXGBE_LINK_SPEED_25GB_FULL      0x10
#define TXGBE_LINK_SPEED_40GB_FULL      0x20

#define TXGBE_SFF_IDENTIFIER_SFP        0x3
#define TXGBE_SFF_IDENTIFIER_QSFP       0xC
#define TXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
#define TXGBE_SFF_IDENTIFIER_QSFP28     0x11
#define TXGBE_SFF_DA_PASSIVE_CABLE      0x4
#define TXGBE_SFF_DA_ACTIVE_CABLE       0x8
#define TXGBE_SFF_DA_SPEC_ACTIVE_LIMIT  0x4
#define TXGBE_SFF_FCPI4_LIMITING        0x3
#define TXGBE_SFF_10GBASESR_CAPABLE     0x10
#define TXGBE_SFF_10GBASELR_CAPABLE     0x20
#define TXGBE_SFF_25GBASESR_CAPABLE     0x2
#define TXGBE_SFF_25GBASELR_CAPABLE     0x3
#define TXGBE_SFF_25GBASEER_CAPABLE     0x4
#define TXGBE_SFF_25GBASECR_91FEC       0xB
#define TXGBE_SFF_25GBASECR_74FEC       0xC
#define TXGBE_SFF_25GBASECR_NOFEC       0xD
#define TXGBE_SFF_ETHERNET_RSRVD        BIT(7)
#define TXGBE_SFF_ETHERNET_40G_CR4      BIT(3)
#define TXGBE_SFF_ETHERNET_40G_SR4      BIT(2)
#define TXGBE_SFF_ETHERNET_40G_LR4      BIT(1)
#define TXGBE_SFF_ETHERNET_40G_ACTIVE   BIT(0)
#define TXGBE_SFF_ETHERNET_100G_CR4     0xB

#define TXGBE_PHY_FEC_RS                BIT(0)
#define TXGBE_PHY_FEC_BASER             BIT(1)
#define TXGBE_PHY_FEC_OFF               BIT(2)
#define TXGBE_PHY_FEC_AUTO              (TXGBE_PHY_FEC_OFF | \
					 TXGBE_PHY_FEC_BASER |\
					 TXGBE_PHY_FEC_RS)

#define FW_PHY_GET_LINK_CMD             0xC0
#define FW_PHY_SET_LINK_CMD             0xC1
#define FW_GET_MODULE_INFO_CMD          0xC5
#define FW_READ_EEPROM_CMD              0xC6

struct txgbe_sff_id {
	u8 identifier;		/* A0H 0x00 */
	u8 com_1g_code;		/* A0H 0x06 */
	u8 com_10g_code;	/* A0H 0x03 */
	u8 com_25g_code;	/* A0H 0x24 */
	u8 cable_spec;		/* A0H 0x3C */
	u8 cable_tech;		/* A0H 0x08 */
	u8 vendor_oui0;		/* A0H 0x25 */
	u8 vendor_oui1;		/* A0H 0x26 */
	u8 vendor_oui2;		/* A0H 0x27 */
	u8 transceiver_type;	/* A0H 0x83 */
	u8 sff_opt1;		/* A0H 0xC0 */
	u8 reserved[5];
};

struct txgbe_hic_get_module_info {

Annotation

Implementation Notes