drivers/net/ethernet/xilinx/ll_temac.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/xilinx/ll_temac.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/xilinx/ll_temac.h- Extension
.h- Size
- 14041 bytes
- Lines
- 416
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/netdevice.hlinux/of.hlinux/platform_device.hlinux/spinlock.hasm/dcr.hasm/dcr-regs.h
Detected Declarations
struct cdmac_bdstruct temac_local
Annotated Snippet
struct cdmac_bd {
u32 next; /* Physical address of next buffer descriptor */
u32 phys;
u32 len;
u32 app0;
u32 app1; /* TX start << 16 | insert */
u32 app2; /* TX csum */
u32 app3;
u32 app4; /* skb for TX length for RX */
};
struct temac_local {
struct net_device *ndev;
struct device *dev;
/* Connection to PHY device */
struct device_node *phy_node;
/* For non-device-tree devices */
char phy_name[MII_BUS_ID_SIZE + 3];
phy_interface_t phy_interface;
/* MDIO bus data */
struct mii_bus *mii_bus; /* MII bus reference */
/* IO registers, dma functions and IRQs */
void __iomem *regs;
void __iomem *sdma_regs;
#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
#endif
u32 (*temac_ior)(struct temac_local *lp, int offset);
void (*temac_iow)(struct temac_local *lp, int offset, u32 value);
u32 (*dma_in)(struct temac_local *lp, int reg);
void (*dma_out)(struct temac_local *lp, int reg, u32 value);
int tx_irq;
int rx_irq;
int emac_num;
struct sk_buff **rx_skb;
spinlock_t rx_lock;
/* For synchronization of indirect register access. Must be
* shared mutex between interfaces in same TEMAC block.
*/
spinlock_t *indirect_lock;
u32 options; /* Current options word */
int last_link;
unsigned int temac_features;
/* Buffer descriptors */
struct cdmac_bd *tx_bd_v;
dma_addr_t tx_bd_p;
u32 tx_bd_num;
struct cdmac_bd *rx_bd_v;
dma_addr_t rx_bd_p;
u32 rx_bd_num;
int tx_bd_ci;
int tx_bd_tail;
int rx_bd_ci;
int rx_bd_tail;
/* DMA channel control setup */
u8 coalesce_count_tx;
u8 coalesce_delay_tx;
u8 coalesce_count_rx;
u8 coalesce_delay_rx;
struct delayed_work restart_work;
};
/* Wrappers for temac_ior()/temac_iow() function pointers above */
#define temac_ior(lp, o) ((lp)->temac_ior(lp, o))
#define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v))
/* xilinx_temac.c */
int temac_indirect_busywait(struct temac_local *lp);
u32 temac_indirect_in32(struct temac_local *lp, int reg);
u32 temac_indirect_in32_locked(struct temac_local *lp, int reg);
void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value);
/* xilinx_temac_mdio.c */
int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev);
void temac_mdio_teardown(struct temac_local *lp);
#endif /* XILINX_LL_TEMAC_H */
Annotation
- Immediate include surface: `linux/netdevice.h`, `linux/of.h`, `linux/platform_device.h`, `linux/spinlock.h`, `asm/dcr.h`, `asm/dcr-regs.h`.
- Detected declarations: `struct cdmac_bd`, `struct temac_local`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.