drivers/net/fddi/skfp/h/skfbi.h

Source file repositories/reference/linux-study-clean/drivers/net/fddi/skfp/h/skfbi.h

File Facts

System
Linux kernel
Corpus path
drivers/net/fddi/skfp/h/skfbi.h
Extension
.h
Size
37804 bytes
Lines
897
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef	_SKFBI_H_
#define	_SKFBI_H_

/*
 * FDDI-Fx (x := {I(SA), P(CI)})
 *	address calculation & function defines
 */

/*--------------------------------------------------------------------------*/
#ifdef	PCI

/*
 *	(DV)	= only defined for Da Vinci
 *	(ML)	= only defined for Monalisa
 */


/*
 * I2C Address (PCI Config)
 *
 * Note: The temperature and voltage sensors are relocated on a different
 *	 I2C bus.
 */
#define I2C_ADDR_VPD	0xA0	/* I2C address for the VPD EEPROM */ 

/*
 *	Control Register File:
 *	Bank 0
 */
#define	B0_RAP		0x0000	/*  8 bit register address port */
	/* 0x0001 - 0x0003:	reserved */
#define	B0_CTRL		0x0004	/*  8 bit control register */
#define	B0_DAS		0x0005	/*  8 Bit control register (DAS) */
#define	B0_LED		0x0006	/*  8 Bit LED register */
#define	B0_TST_CTRL	0x0007	/*  8 bit test control register */
#define	B0_ISRC		0x0008	/* 32 bit Interrupt source register */
#define	B0_IMSK		0x000c	/* 32 bit Interrupt mask register */

/* 0x0010 - 0x006b:	formac+ (supernet_3) fequently used registers */
#define B0_CMDREG1	0x0010	/* write command reg 1 instruction */
#define B0_CMDREG2	0x0014	/* write command reg 2 instruction */
#define B0_ST1U		0x0010	/* read upper 16-bit of status reg 1 */
#define B0_ST1L		0x0014	/* read lower 16-bit of status reg 1 */
#define B0_ST2U		0x0018	/* read upper 16-bit of status reg 2 */
#define B0_ST2L		0x001c	/* read lower 16-bit of status reg 2 */

#define B0_MARR		0x0020	/* r/w the memory read addr register */
#define B0_MARW		0x0024	/* r/w the memory write addr register*/
#define B0_MDRU		0x0028	/* r/w upper 16-bit of mem. data reg */
#define B0_MDRL		0x002c	/* r/w lower 16-bit of mem. data reg */

#define	B0_MDREG3	0x0030	/* r/w Mode Register 3 */
#define	B0_ST3U		0x0034	/* read upper 16-bit of status reg 3 */
#define	B0_ST3L		0x0038	/* read lower 16-bit of status reg 3 */
#define	B0_IMSK3U	0x003c	/* r/w upper 16-bit of IMSK reg 3 */
#define	B0_IMSK3L	0x0040	/* r/w lower 16-bit of IMSK reg 3 */
#define	B0_IVR		0x0044	/* read Interrupt Vector register */
#define	B0_IMR		0x0048	/* r/w Interrupt mask register */
/* 0x4c	Hidden */

#define B0_CNTRL_A	0x0050	/* control register A (r/w) */
#define B0_CNTRL_B	0x0054	/* control register B (r/w) */
#define B0_INTR_MASK	0x0058	/* interrupt mask (r/w) */
#define B0_XMIT_VECTOR	0x005c	/* transmit vector register (r/w) */

#define B0_STATUS_A	0x0060	/* status register A (read only) */
#define B0_STATUS_B	0x0064	/* status register B (read only) */
#define B0_CNTRL_C	0x0068	/* control register C (r/w) */
#define	B0_MDREG1	0x006c	/* r/w Mode Register 1 */

#define	B0_R1_CSR	0x0070	/* 32 bit BMU control/status reg (rec q 1) */
#define	B0_R2_CSR	0x0074	/* 32 bit BMU control/status reg (rec q 2)(DV)*/
#define	B0_XA_CSR	0x0078	/* 32 bit BMU control/status reg (a xmit q) */
#define	B0_XS_CSR	0x007c	/* 32 bit BMU control/status reg (s xmit q) */

/*
 *	Bank 1
 *	- completely empty (this is the RAP Block window)
 *	Note: if RAP = 1 this page is reserved
 */

/*
 *	Bank 2
 */
#define	B2_MAC_0	0x0100	/*  8 bit MAC address Byte 0 */
#define	B2_MAC_1	0x0101	/*  8 bit MAC address Byte 1 */
#define	B2_MAC_2	0x0102	/*  8 bit MAC address Byte 2 */
#define	B2_MAC_3	0x0103	/*  8 bit MAC address Byte 3 */
#define	B2_MAC_4	0x0104	/*  8 bit MAC address Byte 4 */
#define	B2_MAC_5	0x0105	/*  8 bit MAC address Byte 5 */

Annotation

Implementation Notes