drivers/net/fddi/skfp/h/supern_2.h

Source file repositories/reference/linux-study-clean/drivers/net/fddi/skfp/h/supern_2.h

File Facts

System
Linux kernel
Corpus path
drivers/net/fddi/skfp/h/supern_2.h
Extension
.h
Size
45648 bytes
Lines
1056
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct t {
#ifdef	LITTLE_ENDIAN
	unsigned int	tp_pointer:16 ;	/* pointer to tx_descr (low/high) */
	unsigned int	tp_res	  :8 ;	/* reserved 	 (bit 16..23) */
	unsigned int	tp_pattern:8 ;	/* fixed pattern (bit 24..31) */
#else
	unsigned int	tp_pattern:8 ;	/* fixed pattern (bit 24..31) */
	unsigned int	tp_res	  :8 ;	/* reserved 	 (bit 16..23) */
	unsigned int	tp_pointer:16 ;	/* pointer to tx_descr (low/high) */
#endif
	} t ;
	long	i ;
} ;

/* defines for Nontag Mode Pointer access */
#define	TD_P_CNTRL	0xff000000L
#define TD_P_RPXU	0x0000ff00L
#define TD_P_RPXL	0x000000ffL
#define TD_P_RPX	0x0000ffffL


#define TX_PATTERN	0xa0
#define TX_POINTER_END	0xa0000000L
#define TX_INT_PATTERN	0xa0000000L

struct tx_queue {
	struct tx_queue *tq_next ;
	u_short tq_pack_offset ;	/* offset buffer memory */
	u_char  tq_pad[2] ;
} ;

/*
	defines for FORMAC Plus (Am79C830)
*/

/*
 *  FORMAC+ read/write (r/w) registers
 */
#define FM_CMDREG1	0x00		/* write command reg 1 instruction */
#define FM_CMDREG2	0x01		/* write command reg 2 instruction */
#define FM_ST1U		0x00		/* read upper 16-bit of status reg 1 */
#define FM_ST1L		0x01		/* read lower 16-bit of status reg 1 */
#define FM_ST2U		0x02		/* read upper 16-bit of status reg 2 */
#define FM_ST2L		0x03		/* read lower 16-bit of status reg 2 */
#define FM_IMSK1U	0x04		/* r/w upper 16-bit of IMSK 1 */
#define FM_IMSK1L	0x05		/* r/w lower 16-bit of IMSK 1 */
#define FM_IMSK2U	0x06		/* r/w upper 16-bit of IMSK 2 */
#define FM_IMSK2L	0x07		/* r/w lower 16-bit of IMSK 2 */
#define FM_SAID		0x08		/* r/w short addr.-individual */
#define FM_LAIM		0x09		/* r/w long addr.-ind. (MSW of LAID) */
#define FM_LAIC		0x0a		/* r/w long addr.-ind. (middle)*/
#define FM_LAIL		0x0b		/* r/w long addr.-ind. (LSW) */
#define FM_SAGP		0x0c		/* r/w short address-group */
#define FM_LAGM		0x0d		/* r/w long addr.-gr. (MSW of LAGP) */
#define FM_LAGC		0x0e		/* r/w long addr.-gr. (middle) */
#define FM_LAGL		0x0f		/* r/w long addr.-gr. (LSW) */
#define FM_MDREG1	0x10		/* r/w 16-bit mode reg 1 */
#define FM_STMCHN	0x11		/* read state-machine reg */
#define FM_MIR1		0x12		/* read upper 16-bit of MAC Info Reg */
#define FM_MIR0		0x13		/* read lower 16-bit of MAC Info Reg */
#define FM_TMAX		0x14		/* r/w 16-bit TMAX reg */
#define FM_TVX		0x15		/* write 8-bit TVX reg with NP7-0
					   read TVX on NP7-0, timer on NP15-8*/
#define FM_TRT		0x16		/* r/w upper 16-bit of TRT timer */
#define FM_THT		0x17		/* r/w upper 16-bit of THT timer */
#define FM_TNEG		0x18		/* read upper 16-bit of TNEG (TTRT) */
#define FM_TMRS		0x19		/* read lower 5-bit of TNEG,TRT,THT */
			/* F E D C  B A 9 8  7 6 5 4  3 2 1 0
			   x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
#define FM_TREQ0	0x1a		/* r/w 16-bit TREQ0 reg (LSW of TRT) */
#define FM_TREQ1	0x1b		/* r/w 16-bit TREQ1 reg (MSW of TRT) */
#define FM_PRI0		0x1c		/* r/w priority r. for asyn.-queue 0 */
#define FM_PRI1		0x1d		/* r/w priority r. for asyn.-queue 1 */
#define FM_PRI2		0x1e		/* r/w priority r. for asyn.-queue 2 */
#define FM_TSYNC	0x1f		/* r/w 16-bit of the TSYNC register */
#define FM_MDREG2	0x20		/* r/w 16-bit mode reg 2 */
#define FM_FRMTHR	0x21		/* r/w the frame threshold register */
#define FM_EACB		0x22		/* r/w end addr of claim/beacon area */
#define FM_EARV		0x23		/* r/w end addr of receive queue */
/* Supernet 3 */
#define	FM_EARV1	FM_EARV

#define FM_EAS		0x24		/* r/w end addr of synchr. queue */
#define FM_EAA0		0x25		/* r/w end addr of asyn. queue 0 */
#define FM_EAA1		0x26		/* r/w end addr of asyn. queue 1 */
#define FM_EAA2		0x27		/* r/w end addr of asyn. queue 2 */
#define FM_SACL		0x28		/* r/w start addr of claim frame */
#define FM_SABC		0x29		/* r/w start addr of beacon frame */
#define FM_WPXSF	0x2a		/* r/w the write ptr. for special fr.*/
#define FM_RPXSF	0x2b		/* r/w the read ptr. for special fr. */

Annotation

Implementation Notes