drivers/net/ieee802154/at86rf230.h

Source file repositories/reference/linux-study-clean/drivers/net/ieee802154/at86rf230.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ieee802154/at86rf230.h
Extension
.h
Size
7081 bytes
Lines
221
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _AT86RF230_H
#define _AT86RF230_H

#define RG_TRX_STATUS	(0x01)
#define SR_TRX_STATUS		0x01, 0x1f, 0
#define SR_RESERVED_01_3	0x01, 0x20, 5
#define SR_CCA_STATUS		0x01, 0x40, 6
#define SR_CCA_DONE		0x01, 0x80, 7
#define RG_TRX_STATE	(0x02)
#define SR_TRX_CMD		0x02, 0x1f, 0
#define SR_TRAC_STATUS		0x02, 0xe0, 5
#define RG_TRX_CTRL_0	(0x03)
#define SR_CLKM_CTRL		0x03, 0x07, 0
#define SR_CLKM_SHA_SEL		0x03, 0x08, 3
#define SR_PAD_IO_CLKM		0x03, 0x30, 4
#define SR_PAD_IO		0x03, 0xc0, 6
#define RG_TRX_CTRL_1	(0x04)
#define SR_IRQ_POLARITY		0x04, 0x01, 0
#define SR_IRQ_MASK_MODE	0x04, 0x02, 1
#define SR_SPI_CMD_MODE		0x04, 0x0c, 2
#define SR_RX_BL_CTRL		0x04, 0x10, 4
#define SR_TX_AUTO_CRC_ON	0x04, 0x20, 5
#define SR_IRQ_2_EXT_EN		0x04, 0x40, 6
#define SR_PA_EXT_EN		0x04, 0x80, 7
#define RG_PHY_TX_PWR	(0x05)
#define SR_TX_PWR_23X		0x05, 0x0f, 0
#define SR_PA_LT_230		0x05, 0x30, 4
#define SR_PA_BUF_LT_230	0x05, 0xc0, 6
#define SR_TX_PWR_212		0x05, 0x1f, 0
#define SR_GC_PA_212		0x05, 0x60, 5
#define SR_PA_BOOST_LT_212	0x05, 0x80, 7
#define RG_PHY_RSSI	(0x06)
#define SR_RSSI			0x06, 0x1f, 0
#define SR_RND_VALUE		0x06, 0x60, 5
#define SR_RX_CRC_VALID		0x06, 0x80, 7
#define RG_PHY_ED_LEVEL	(0x07)
#define SR_ED_LEVEL		0x07, 0xff, 0
#define RG_PHY_CC_CCA	(0x08)
#define SR_CHANNEL		0x08, 0x1f, 0
#define SR_CCA_MODE		0x08, 0x60, 5
#define SR_CCA_REQUEST		0x08, 0x80, 7
#define RG_CCA_THRES	(0x09)
#define SR_CCA_ED_THRES		0x09, 0x0f, 0
#define SR_RESERVED_09_1	0x09, 0xf0, 4
#define RG_RX_CTRL	(0x0a)
#define SR_PDT_THRES		0x0a, 0x0f, 0
#define SR_RESERVED_0a_1	0x0a, 0xf0, 4
#define RG_SFD_VALUE	(0x0b)
#define SR_SFD_VALUE		0x0b, 0xff, 0
#define RG_TRX_CTRL_2	(0x0c)
#define SR_OQPSK_DATA_RATE	0x0c, 0x03, 0
#define SR_SUB_MODE		0x0c, 0x04, 2
#define SR_BPSK_QPSK		0x0c, 0x08, 3
#define SR_OQPSK_SUB1_RC_EN	0x0c, 0x10, 4
#define SR_RESERVED_0c_5	0x0c, 0x60, 5
#define SR_RX_SAFE_MODE		0x0c, 0x80, 7
#define RG_ANT_DIV	(0x0d)
#define SR_ANT_CTRL		0x0d, 0x03, 0
#define SR_ANT_EXT_SW_EN	0x0d, 0x04, 2
#define SR_ANT_DIV_EN		0x0d, 0x08, 3
#define SR_RESERVED_0d_2	0x0d, 0x70, 4
#define SR_ANT_SEL		0x0d, 0x80, 7
#define RG_IRQ_MASK	(0x0e)
#define SR_IRQ_MASK		0x0e, 0xff, 0
#define RG_IRQ_STATUS	(0x0f)
#define SR_IRQ_0_PLL_LOCK	0x0f, 0x01, 0
#define SR_IRQ_1_PLL_UNLOCK	0x0f, 0x02, 1
#define SR_IRQ_2_RX_START	0x0f, 0x04, 2
#define SR_IRQ_3_TRX_END	0x0f, 0x08, 3
#define SR_IRQ_4_CCA_ED_DONE	0x0f, 0x10, 4
#define SR_IRQ_5_AMI		0x0f, 0x20, 5
#define SR_IRQ_6_TRX_UR		0x0f, 0x40, 6
#define SR_IRQ_7_BAT_LOW	0x0f, 0x80, 7
#define RG_VREG_CTRL	(0x10)
#define SR_RESERVED_10_6	0x10, 0x03, 0
#define SR_DVDD_OK		0x10, 0x04, 2
#define SR_DVREG_EXT		0x10, 0x08, 3
#define SR_RESERVED_10_3	0x10, 0x30, 4
#define SR_AVDD_OK		0x10, 0x40, 6
#define SR_AVREG_EXT		0x10, 0x80, 7
#define RG_BATMON	(0x11)
#define SR_BATMON_VTH		0x11, 0x0f, 0
#define SR_BATMON_HR		0x11, 0x10, 4
#define SR_BATMON_OK		0x11, 0x20, 5
#define SR_RESERVED_11_1	0x11, 0xc0, 6
#define RG_XOSC_CTRL	(0x12)
#define SR_XTAL_TRIM		0x12, 0x0f, 0
#define SR_XTAL_MODE		0x12, 0xf0, 4
#define RG_RX_SYN	(0x15)
#define SR_RX_PDT_LEVEL		0x15, 0x0f, 0

Annotation

Implementation Notes