drivers/net/ieee802154/mcr20a.h
Source file repositories/reference/linux-study-clean/drivers/net/ieee802154/mcr20a.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ieee802154/mcr20a.h- Extension
.h- Size
- 15466 bytes
- Lines
- 490
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _MCR20A_H
#define _MCR20A_H
/* Direct Accress Register */
#define DAR_IRQ_STS1 0x00
#define DAR_IRQ_STS2 0x01
#define DAR_IRQ_STS3 0x02
#define DAR_PHY_CTRL1 0x03
#define DAR_PHY_CTRL2 0x04
#define DAR_PHY_CTRL3 0x05
#define DAR_RX_FRM_LEN 0x06
#define DAR_PHY_CTRL4 0x07
#define DAR_SRC_CTRL 0x08
#define DAR_SRC_ADDRS_SUM_LSB 0x09
#define DAR_SRC_ADDRS_SUM_MSB 0x0A
#define DAR_CCA1_ED_FNL 0x0B
#define DAR_EVENT_TMR_LSB 0x0C
#define DAR_EVENT_TMR_MSB 0x0D
#define DAR_EVENT_TMR_USB 0x0E
#define DAR_TIMESTAMP_LSB 0x0F
#define DAR_TIMESTAMP_MSB 0x10
#define DAR_TIMESTAMP_USB 0x11
#define DAR_T3CMP_LSB 0x12
#define DAR_T3CMP_MSB 0x13
#define DAR_T3CMP_USB 0x14
#define DAR_T2PRIMECMP_LSB 0x15
#define DAR_T2PRIMECMP_MSB 0x16
#define DAR_T1CMP_LSB 0x17
#define DAR_T1CMP_MSB 0x18
#define DAR_T1CMP_USB 0x19
#define DAR_T2CMP_LSB 0x1A
#define DAR_T2CMP_MSB 0x1B
#define DAR_T2CMP_USB 0x1C
#define DAR_T4CMP_LSB 0x1D
#define DAR_T4CMP_MSB 0x1E
#define DAR_T4CMP_USB 0x1F
#define DAR_PLL_INT0 0x20
#define DAR_PLL_FRAC0_LSB 0x21
#define DAR_PLL_FRAC0_MSB 0x22
#define DAR_PA_PWR 0x23
#define DAR_SEQ_STATE 0x24
#define DAR_LQI_VALUE 0x25
#define DAR_RSSI_CCA_CONT 0x26
/*------------------ 0x27 */
#define DAR_ASM_CTRL1 0x28
#define DAR_ASM_CTRL2 0x29
#define DAR_ASM_DATA_0 0x2A
#define DAR_ASM_DATA_1 0x2B
#define DAR_ASM_DATA_2 0x2C
#define DAR_ASM_DATA_3 0x2D
#define DAR_ASM_DATA_4 0x2E
#define DAR_ASM_DATA_5 0x2F
#define DAR_ASM_DATA_6 0x30
#define DAR_ASM_DATA_7 0x31
#define DAR_ASM_DATA_8 0x32
#define DAR_ASM_DATA_9 0x33
#define DAR_ASM_DATA_A 0x34
#define DAR_ASM_DATA_B 0x35
#define DAR_ASM_DATA_C 0x36
#define DAR_ASM_DATA_D 0x37
#define DAR_ASM_DATA_E 0x38
#define DAR_ASM_DATA_F 0x39
/*----------------------- 0x3A */
#define DAR_OVERWRITE_VER 0x3B
#define DAR_CLK_OUT_CTRL 0x3C
#define DAR_PWR_MODES 0x3D
#define IAR_INDEX 0x3E
#define IAR_DATA 0x3F
/* Indirect Resgister Memory */
#define IAR_PART_ID 0x00
#define IAR_XTAL_TRIM 0x01
#define IAR_PMC_LP_TRIM 0x02
#define IAR_MACPANID0_LSB 0x03
#define IAR_MACPANID0_MSB 0x04
#define IAR_MACSHORTADDRS0_LSB 0x05
#define IAR_MACSHORTADDRS0_MSB 0x06
#define IAR_MACLONGADDRS0_0 0x07
#define IAR_MACLONGADDRS0_8 0x08
#define IAR_MACLONGADDRS0_16 0x09
#define IAR_MACLONGADDRS0_24 0x0A
#define IAR_MACLONGADDRS0_32 0x0B
#define IAR_MACLONGADDRS0_40 0x0C
#define IAR_MACLONGADDRS0_48 0x0D
#define IAR_MACLONGADDRS0_56 0x0E
#define IAR_RX_FRAME_FILTER 0x0F
#define IAR_PLL_INT1 0x10
#define IAR_PLL_FRAC1_LSB 0x11
#define IAR_PLL_FRAC1_MSB 0x12
#define IAR_MACPANID1_LSB 0x13
Annotation
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.