drivers/net/ieee802154/mrf24j40.c

Source file repositories/reference/linux-study-clean/drivers/net/ieee802154/mrf24j40.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ieee802154/mrf24j40.c
Extension
.c
Size
36418 bytes
Lines
1402
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mrf24j40 {
	struct spi_device *spi;
	struct ieee802154_hw *hw;

	struct regmap *regmap_short;
	struct regmap *regmap_long;

	/* for writing txfifo */
	struct spi_message tx_msg;
	u8 tx_hdr_buf[2];
	struct spi_transfer tx_hdr_trx;
	u8 tx_len_buf[2];
	struct spi_transfer tx_len_trx;
	struct spi_transfer tx_buf_trx;
	struct sk_buff *tx_skb;

	/* post transmit message to send frame out  */
	struct spi_message tx_post_msg;
	u8 tx_post_buf[2];
	struct spi_transfer tx_post_trx;

	/* for protect/unprotect/read length rxfifo */
	struct spi_message rx_msg;
	u8 rx_buf[3];
	struct spi_transfer rx_trx;

	/* receive handling */
	struct spi_message rx_buf_msg;
	u8 rx_addr_buf[2];
	struct spi_transfer rx_addr_trx;
	u8 rx_lqi_buf[2];
	struct spi_transfer rx_lqi_trx;
	u8 rx_fifo_buf[RX_FIFO_SIZE];
	struct spi_transfer rx_fifo_buf_trx;

	/* isr handling for reading intstat */
	struct spi_message irq_msg;
	u8 irq_buf[2];
	struct spi_transfer irq_trx;
};

/* regmap information for short address register access */
#define MRF24J40_SHORT_WRITE	0x01
#define MRF24J40_SHORT_READ	0x00
#define MRF24J40_SHORT_NUMREGS	0x3F

/* regmap information for long address register access */
#define MRF24J40_LONG_ACCESS	0x80
#define MRF24J40_LONG_NUMREGS	0x38F

/* Read/Write SPI Commands for Short and Long Address registers. */
#define MRF24J40_READSHORT(reg) ((reg) << 1)
#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)

/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
#define MAX_SPI_SPEED_HZ 10000000

#define printdev(X) (&X->spi->dev)

static bool
mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case REG_RXMCR:
	case REG_PANIDL:
	case REG_PANIDH:
	case REG_SADRL:
	case REG_SADRH:
	case REG_EADR0:
	case REG_EADR1:
	case REG_EADR2:
	case REG_EADR3:
	case REG_EADR4:
	case REG_EADR5:
	case REG_EADR6:
	case REG_EADR7:
	case REG_RXFLUSH:
	case REG_ORDER:
	case REG_TXMCR:
	case REG_ACKTMOUT:
	case REG_ESLOTG1:
	case REG_SYMTICKL:
	case REG_SYMTICKH:
	case REG_PACON0:
	case REG_PACON1:
	case REG_PACON2:
	case REG_TXBCON0:
	case REG_TXNCON:

Annotation

Implementation Notes