drivers/net/phy/dp83640_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/phy/dp83640_reg.h

File Facts

System: Linux kernel
Corpus path: drivers/net/phy/dp83640_reg.h
Extension: .h
Size: 16362 bytes
Lines: 269
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef HAVE_DP83640_REGISTERS
#define HAVE_DP83640_REGISTERS

/* #define PAGE0                  0x0000 */
#define PHYCR2                    0x001c /* PHY Control Register 2 */

#define PAGE4                     0x0004
#define PTP_CTL                   0x0014 /* PTP Control Register */
#define PTP_TDR                   0x0015 /* PTP Time Data Register */
#define PTP_STS                   0x0016 /* PTP Status Register */
#define PTP_TSTS                  0x0017 /* PTP Trigger Status Register */
#define PTP_RATEL                 0x0018 /* PTP Rate Low Register */
#define PTP_RATEH                 0x0019 /* PTP Rate High Register */
#define PTP_RDCKSUM               0x001a /* PTP Read Checksum */
#define PTP_WRCKSUM               0x001b /* PTP Write Checksum */
#define PTP_TXTS                  0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
#define PTP_RXTS                  0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
#define PTP_ESTS                  0x001e /* PTP Event Status Register */
#define PTP_EDATA                 0x001f /* PTP Event Data Register */

#define PAGE5                     0x0005
#define PTP_TRIG                  0x0014 /* PTP Trigger Configuration Register */
#define PTP_EVNT                  0x0015 /* PTP Event Configuration Register */
#define PTP_TXCFG0                0x0016 /* PTP Transmit Configuration Register 0 */
#define PTP_TXCFG1                0x0017 /* PTP Transmit Configuration Register 1 */
#define PSF_CFG0                  0x0018 /* PHY Status Frame Configuration Register 0 */
#define PTP_RXCFG0                0x0019 /* PTP Receive Configuration Register 0 */
#define PTP_RXCFG1                0x001a /* PTP Receive Configuration Register 1 */
#define PTP_RXCFG2                0x001b /* PTP Receive Configuration Register 2 */
#define PTP_RXCFG3                0x001c /* PTP Receive Configuration Register 3 */
#define PTP_RXCFG4                0x001d /* PTP Receive Configuration Register 4 */
#define PTP_TRDL                  0x001e /* PTP Temporary Rate Duration Low Register */
#define PTP_TRDH                  0x001f /* PTP Temporary Rate Duration High Register */

#define PAGE6                     0x0006
#define PTP_COC                   0x0014 /* PTP Clock Output Control Register */
#define PSF_CFG1                  0x0015 /* PHY Status Frame Configuration Register 1 */
#define PSF_CFG2                  0x0016 /* PHY Status Frame Configuration Register 2 */
#define PSF_CFG3                  0x0017 /* PHY Status Frame Configuration Register 3 */
#define PSF_CFG4                  0x0018 /* PHY Status Frame Configuration Register 4 */
#define PTP_SFDCFG                0x0019 /* PTP SFD Configuration Register */
#define PTP_INTCTL                0x001a /* PTP Interrupt Control Register */
#define PTP_CLKSRC                0x001b /* PTP Clock Source Register */
#define PTP_ETR                   0x001c /* PTP Ethernet Type Register */
#define PTP_OFF                   0x001d /* PTP Offset Register */
#define PTP_GPIOMON               0x001e /* PTP GPIO Monitor Register */
#define PTP_RXHASH                0x001f /* PTP Receive Hash Register */

/* Bit definitions for the PHYCR2 register */
#define BC_WRITE                  (1<<11) /* Broadcast Write Enable */

/* Bit definitions for the PTP_CTL register */
#define TRIG_SEL_SHIFT            (10)    /* PTP Trigger Select */
#define TRIG_SEL_MASK             (0x7)
#define TRIG_DIS                  (1<<9)  /* Disable PTP Trigger */
#define TRIG_EN                   (1<<8)  /* Enable PTP Trigger */
#define TRIG_READ                 (1<<7)  /* Read PTP Trigger */
#define TRIG_LOAD                 (1<<6)  /* Load PTP Trigger */
#define PTP_RD_CLK                (1<<5)  /* Read PTP Clock */
#define PTP_LOAD_CLK              (1<<4)  /* Load PTP Clock */
#define PTP_STEP_CLK              (1<<3)  /* Step PTP Clock */
#define PTP_ENABLE                (1<<2)  /* Enable PTP Clock */
#define PTP_DISABLE               (1<<1)  /* Disable PTP Clock */
#define PTP_RESET                 (1<<0)  /* Reset PTP Clock */

/* Bit definitions for the PTP_STS register */
#define TXTS_RDY                  (1<<11) /* Transmit Timestamp Ready */
#define RXTS_RDY                  (1<<10) /* Receive Timestamp Ready */
#define TRIG_DONE                 (1<<9)  /* PTP Trigger Done */
#define EVENT_RDY                 (1<<8)  /* PTP Event Timestamp Ready */
#define TXTS_IE                   (1<<3)  /* Transmit Timestamp Interrupt Enable */
#define RXTS_IE                   (1<<2)  /* Receive Timestamp Interrupt Enable */
#define TRIG_IE                   (1<<1)  /* Trigger Interrupt Enable */
#define EVENT_IE                  (1<<0)  /* Event Interrupt Enable */

/* Bit definitions for the PTP_TSTS register */
#define TRIG7_ERROR               (1<<15) /* Trigger 7 Error */
#define TRIG7_ACTIVE              (1<<14) /* Trigger 7 Active */
#define TRIG6_ERROR               (1<<13) /* Trigger 6 Error */
#define TRIG6_ACTIVE              (1<<12) /* Trigger 6 Active */
#define TRIG5_ERROR               (1<<11) /* Trigger 5 Error */
#define TRIG5_ACTIVE              (1<<10) /* Trigger 5 Active */
#define TRIG4_ERROR               (1<<9)  /* Trigger 4 Error */
#define TRIG4_ACTIVE              (1<<8)  /* Trigger 4 Active */
#define TRIG3_ERROR               (1<<7)  /* Trigger 3 Error */
#define TRIG3_ACTIVE              (1<<6)  /* Trigger 3 Active */
#define TRIG2_ERROR               (1<<5)  /* Trigger 2 Error */
#define TRIG2_ACTIVE              (1<<4)  /* Trigger 2 Active */
#define TRIG1_ERROR               (1<<3)  /* Trigger 1 Error */
#define TRIG1_ACTIVE              (1<<2)  /* Trigger 1 Active */

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.