drivers/net/phy/dp83td510.c

Source file repositories/reference/linux-study-clean/drivers/net/phy/dp83td510.c

File Facts

System
Linux kernel
Corpus path
drivers/net/phy/dp83td510.c
Extension
.c
Size
30385 bytes
Lines
978
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dp83td510_stats {
	u64 tx_pkt_cnt;
	u64 tx_err_pkt_cnt;
	u64 rx_pkt_cnt;
	u64 rx_err_pkt_cnt;
};

struct dp83td510_priv {
	bool alcd_test_active;
	struct dp83td510_stats stats;
};

/* Time Domain Reflectometry (TDR) Functionality of DP83TD510 PHY
 *
 * I assume that this PHY is using a variation of Spread Spectrum Time Domain
 * Reflectometry (SSTDR) rather than the commonly used TDR found in many PHYs.
 * Here are the following observations which likely confirm this:
 * - The DP83TD510 PHY transmits a modulated signal of configurable length
 *   (default 16000 µs) instead of a single pulse pattern, which is typical
 *   for traditional TDR.
 * - The pulse observed on the wire, triggered by the HW RESET register, is not
 *   part of the cable testing process.
 *
 * I assume that SSTDR seems to be a logical choice for the 10BaseT1L
 * environment due to improved noise resistance, making it suitable for
 * environments  with significant electrical noise, such as long 10BaseT1L cable
 * runs.
 *
 * Configuration Variables:
 * The SSTDR variation used in this PHY involves more configuration variables
 * that can dramatically affect the functionality and precision of cable
 * testing. Since most of  these configuration options are either not well
 * documented or documented with minimal details, the following sections
 * describe my understanding and observations of these variables and their
 * impact on TDR functionality.
 *
 * Timeline:
 *     ,<--cfg_pre_silence_time
 *     |            ,<-SSTDR Modulated Transmission
 *     |	    |            ,<--cfg_post_silence_time
 *     |	    |            |             ,<--Force Link Mode
 * |<--'-->|<-------'------->|<--'-->|<--------'------->|
 *
 * - cfg_pre_silence_time: Optional silence time before TDR transmission starts.
 * - SSTDR Modulated Transmission: Transmission duration configured by
 *   cfg_tdr_tx_duration and amplitude configured by cfg_tdr_tx_type.
 * - cfg_post_silence_time: Silence time after TDR transmission.
 * - Force Link Mode: If nothing is configured after cfg_post_silence_time,
 *   the PHY continues in force link mode without autonegotiation.
 */

#define DP83TD510E_TDR_CFG				0x1e
#define DP83TD510E_TDR_START				BIT(15)
#define DP83TD510E_TDR_DONE				BIT(1)
#define DP83TD510E_TDR_FAIL				BIT(0)

#define DP83TD510E_TDR_CFG1				0x300
/* cfg_tdr_tx_type: Transmit voltage level for TDR.
 * 0 = 1V, 1 = 2.4V
 * Note: Using different voltage levels may not work
 * in all configuration variations. For example, setting
 * 2.4V may give different cable length measurements.
 * Other settings may be needed to make it work properly.
 */
#define DP83TD510E_TDR_TX_TYPE				BIT(12)
#define DP83TD510E_TDR_TX_TYPE_1V			0
#define DP83TD510E_TDR_TX_TYPE_2_4V			1
/* cfg_post_silence_time: Time after the TDR sequence. Since we force master mode
 * for the TDR will proceed with forced link state after this time. For Linux
 * it is better to set max value to avoid false link state detection.
 */
#define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME		GENMASK(3, 2)
#define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_0MS	0
#define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_10MS	1
#define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_100MS	2
#define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS	3
/* cfg_pre_silence_time: Time before the TDR sequence. It should be enough to
 * settle down all pulses and reflections. Since for 10BASE-T1L we have
 * maximum 2000m cable length, we can set it to 1ms.
 */
#define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME		GENMASK(1, 0)
#define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_0MS	0
#define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS	1
#define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_100MS	2
#define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_1000MS	3

#define DP83TD510E_TDR_CFG2				0x301
#define DP83TD510E_TDR_END_TAP_INDEX_1			GENMASK(14, 8)
#define DP83TD510E_TDR_END_TAP_INDEX_1_DEF		36
#define DP83TD510E_TDR_START_TAP_INDEX_1		GENMASK(6, 0)

Annotation

Implementation Notes