drivers/net/phy/mscc/mscc_macsec.h

Source file repositories/reference/linux-study-clean/drivers/net/phy/mscc/mscc_macsec.h

File Facts

System
Linux kernel
Corpus path
drivers/net/phy/mscc/mscc_macsec.h
Extension
.h
Size
12207 bytes
Lines
324
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct macsec_flow {
	struct list_head list;
	enum mscc_macsec_destination_ports port;
	enum macsec_bank bank;
	u32 index;
	int assoc_num;
	bool has_transformation;

	/* Highest takes precedence [0..15] */
	u8 priority;

	union {
		struct macsec_rx_sa *rx_sa;
		struct macsec_tx_sa *tx_sa;
	};

	/* Matching */
	struct {
		u8 sci:1;
		u8 tagged:1;
		u8 untagged:1;
		u8 etype:1;
	} match;

	u16 etype;

	/* Action */
	struct {
		u8 bypass:1;
		u8 drop:1;
	} action;
};

#define MSCC_EXT_PAGE_MACSEC_17		17
#define MSCC_EXT_PAGE_MACSEC_18		18

#define MSCC_EXT_PAGE_MACSEC_19		19
#define MSCC_PHY_MACSEC_19_REG_ADDR(x)	(x)
#define MSCC_PHY_MACSEC_19_TARGET(x)	((x) << 12)
#define MSCC_PHY_MACSEC_19_READ		BIT(14)
#define MSCC_PHY_MACSEC_19_CMD		BIT(15)

#define MSCC_EXT_PAGE_MACSEC_20		20
#define MSCC_PHY_MACSEC_20_TARGET(x)	(x)

#define MSCC_MS_XFORM_REC(x, y)		(((x) << 5) + (y))
#define MSCC_MS_ENA_CFG			0x800
#define MSCC_MS_FC_CFG			0x804
#define MSCC_MS_SAM_MAC_SA_MATCH_LO(x)	(0x1000 + ((x) << 4))
#define MSCC_MS_SAM_MAC_SA_MATCH_HI(x)	(0x1001 + ((x) << 4))
#define MSCC_MS_SAM_MISC_MATCH(x)	(0x1004 + ((x) << 4))
#define MSCC_MS_SAM_MATCH_SCI_LO(x)	(0x1005 + ((x) << 4))
#define MSCC_MS_SAM_MATCH_SCI_HI(x)	(0x1006 + ((x) << 4))
#define MSCC_MS_SAM_MASK(x)		(0x1007 + ((x) << 4))
#define MSCC_MS_SAM_ENTRY_SET1		0x1808
#define MSCC_MS_SAM_ENTRY_CLEAR1	0x180c
#define MSCC_MS_SAM_FLOW_CTRL(x)	(0x1c00 + (x))
#define MSCC_MS_SAM_CP_TAG		0x1e40
#define MSCC_MS_SAM_NM_FLOW_NCP		0x1e51
#define MSCC_MS_SAM_NM_FLOW_CP		0x1e52
#define MSCC_MS_MISC_CONTROL		0x1e5f
#define MSCC_MS_COUNT_CONTROL		0x3204
#define MSCC_MS_PARAMS2_IG_CC_CONTROL	0x3a10
#define MSCC_MS_PARAMS2_IG_CP_TAG	0x3a14
#define MSCC_MS_VLAN_MTU_CHECK(x)	(0x3c40 + (x))
#define MSCC_MS_NON_VLAN_MTU_CHECK	0x3c48
#define MSCC_MS_PP_CTRL			0x3c4b
#define MSCC_MS_STATUS_CONTEXT_CTRL	0x3d02
#define MSCC_MS_INTR_CTRL_STATUS	0x3d04
#define MSCC_MS_BLOCK_CTX_UPDATE	0x3d0c
#define MSCC_MS_AIC_CTRL		0x3e02

/* MACSEC_ENA_CFG */
#define MSCC_MS_ENA_CFG_CLK_ENA				BIT(0)
#define MSCC_MS_ENA_CFG_SW_RST				BIT(1)
#define MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA		BIT(8)
#define MSCC_MS_ENA_CFG_MACSEC_ENA			BIT(9)
#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(x)		((x) << 10)
#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE_M		GENMASK(12, 10)

/* MACSEC_FC_CFG */
#define MSCC_MS_FC_CFG_FCBUF_ENA			BIT(0)
#define MSCC_MS_FC_CFG_USE_PKT_EXPANSION_INDICATION	BIT(1)
#define MSCC_MS_FC_CFG_LOW_THRESH(x)			((x) << 4)
#define MSCC_MS_FC_CFG_LOW_THRESH_M			GENMASK(7, 4)
#define MSCC_MS_FC_CFG_HIGH_THRESH(x)			((x) << 8)
#define MSCC_MS_FC_CFG_HIGH_THRESH_M			GENMASK(11, 8)
#define MSCC_MS_FC_CFG_LOW_BYTES_VAL(x)			((x) << 12)
#define MSCC_MS_FC_CFG_LOW_BYTES_VAL_M			GENMASK(14, 12)
#define MSCC_MS_FC_CFG_HIGH_BYTES_VAL(x)		((x) << 16)

Annotation

Implementation Notes