drivers/net/phy/mscc/mscc_serdes.c

Source file repositories/reference/linux-study-clean/drivers/net/phy/mscc/mscc_serdes.c

File Facts

System
Linux kernel
Corpus path
drivers/net/phy/mscc/mscc_serdes.c
Extension
.c
Size
16994 bytes
Lines
651
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (ret) {
			dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n",
				__func__, ret);
			return ret;
		}

		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
	} else if ((ret & MAC_CFG_MASK) == MAC_CFG_SGMII) {
		/* SGMII */
		pll_fsm_ctrl_data = 60;
		qrate   = 1;
		if_mode = 1;
		des_bw_ana_val = 3;

		val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
			PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_SGMII_MAC;

		ret = vsc8584_cmd(phydev, val);
		if (ret) {
			dev_err(&phydev->mdio.dev, "%s: SGMII error: %d\n",
				__func__, ret);
			return ret;
		}

		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
	} else {
		dev_err(&phydev->mdio.dev, "%s: invalid mac_if: %x\n",
			__func__, ret);
	}

	ret = phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
	if (ret)
		return ret;
	ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
	if (ret)
		return ret;
	ret = vsc85xx_pll5g_cfg0_wr(phydev, 4);
	if (ret)
		return ret;
	ret = phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_des_cfg_wr(phydev, 6, 2, 5, des_bw_ana_val, 0);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_ib_cfg0_wr(phydev, ib_rtrm_adj, ib_sig_det_clk_sel_mm, 0, 1);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_ib_cfg1_wr(phydev, 8, ib_tsdet_mm, 15, 0, 1);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_common_cfg_wr(phydev, 1, 1, 0, qrate, if_mode, 0);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_ib_cfg2_wr(phydev, 3, 13, 5);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_ib_cfg3_wr(phydev,  0, 31, 1, 31);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_ib_cfg4_wr(phydev, 63, 63, 2, 63);
	if (ret)
		return ret;
	ret = vsc85xx_sd6g_misc_cfg_wr(phydev, 1);
	if (ret)
		return ret;
	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
	if (ret)
		return ret;

	/* 13. Start rcpll_fsm */
	ret = vsc85xx_sd6g_pll_cfg_wr(phydev, 3, pll_fsm_ctrl_data, 1);
	if (ret)
		return ret;
	ret = phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
	if (ret)
		return ret;

	/* 14. Wait for PLL cal to complete */
	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
	do {
		usleep_range(500, 1000);
		ret = phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
		if (ret)
			return ret;
		val32 = vsc85xx_csr_read(phydev, MACRO_CTRL,
					 PHY_S6G_PLL_STATUS);
		/* wait for bit 12 to clear */
	} while (time_before(jiffies, deadline) && (val32 & BIT(12)));

Annotation

Implementation Notes