drivers/net/phy/nxp-c45-tja11xx.c
Source file repositories/reference/linux-study-clean/drivers/net/phy/nxp-c45-tja11xx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/phy/nxp-c45-tja11xx.c- Extension
.c- Size
- 61490 bytes
- Lines
- 2191
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/ethtool.hlinux/ethtool_netlink.hlinux/kernel.hlinux/mii.hlinux/module.hlinux/of.hlinux/phy.hlinux/processor.hlinux/property.hlinux/ptp_classify.hlinux/net_tstamp.hnxp-c45-tja11xx.h
Detected Declarations
struct nxp_c45_phystruct nxp_c45_skb_cbstruct nxp_c45_reg_fieldstruct nxp_c45_hwtsstruct nxp_c45_regmapstruct nxp_c45_phy_statsstruct nxp_c45_phy_datafunction nxp_c45_read_reg_fieldfunction nxp_c45_write_reg_fieldfunction nxp_c45_set_reg_fieldfunction nxp_c45_clear_reg_fieldfunction nxp_c45_poll_txtsfunction _nxp_c45_ptp_gettimex64function nxp_c45_ptp_gettimex64function _nxp_c45_ptp_settime64function nxp_c45_ptp_settime64function nxp_c45_ptp_adjfinefunction nxp_c45_ptp_adjtimefunction nxp_c45_reconstruct_tsfunction nxp_c45_match_tsfunction nxp_c45_get_exttsfunction tja1120_extts_is_validfunction tja1120_get_exttsfunction nxp_c45_read_egress_tsfunction nxp_c45_get_hwtxtsfunction tja1120_egress_ts_is_validfunction tja1120_get_hwtxtsfunction nxp_c45_process_txtsfunction nxp_c45_do_aux_workfunction nxp_c45_gpio_configfunction nxp_c45_perout_enablefunction nxp_c45_set_rising_or_fallingfunction nxp_c45_set_rising_and_fallingfunction nxp_c45_extts_enablefunction nxp_c45_ptp_enablefunction nxp_c45_ptp_verify_pinfunction nxp_c45_init_ptp_clockfunction nxp_c45_txtstampfunction nxp_c45_rxtstampfunction nxp_c45_hwtstamp_getfunction nxp_c45_hwtstamp_setfunction nxp_c45_ts_infofunction nxp_c45_get_sset_countfunction nxp_c45_get_stringsfunction nxp_c45_get_statsfunction nxp_c45_config_enablefunction nxp_c45_start_opfunction nxp_c45_config_intr
Annotated Snippet
struct nxp_c45_skb_cb {
struct ptp_header *header;
unsigned int type;
};
#define NXP_C45_REG_FIELD(_reg, _devad, _offset, _size) \
((struct nxp_c45_reg_field) { \
.reg = _reg, \
.devad = _devad, \
.offset = _offset, \
.size = _size, \
})
struct nxp_c45_reg_field {
u16 reg;
u8 devad;
u8 offset;
u8 size;
};
struct nxp_c45_hwts {
u32 nsec;
u32 sec;
u8 domain_number;
u16 sequence_id;
u8 msg_type;
};
struct nxp_c45_regmap {
/* PTP config regs. */
u16 vend1_ptp_clk_period;
u16 vend1_event_msg_filt;
/* LTC bits and regs. */
struct nxp_c45_reg_field ltc_read;
struct nxp_c45_reg_field ltc_write;
struct nxp_c45_reg_field ltc_lock_ctrl;
u16 vend1_ltc_wr_nsec_0;
u16 vend1_ltc_wr_nsec_1;
u16 vend1_ltc_wr_sec_0;
u16 vend1_ltc_wr_sec_1;
u16 vend1_ltc_rd_nsec_0;
u16 vend1_ltc_rd_nsec_1;
u16 vend1_ltc_rd_sec_0;
u16 vend1_ltc_rd_sec_1;
u16 vend1_rate_adj_subns_0;
u16 vend1_rate_adj_subns_1;
/* External trigger reg fields. */
struct nxp_c45_reg_field irq_egr_ts_en;
struct nxp_c45_reg_field irq_egr_ts_status;
struct nxp_c45_reg_field domain_number;
struct nxp_c45_reg_field msg_type;
struct nxp_c45_reg_field sequence_id;
struct nxp_c45_reg_field sec_1_0;
struct nxp_c45_reg_field sec_4_2;
struct nxp_c45_reg_field nsec_15_0;
struct nxp_c45_reg_field nsec_29_16;
/* PPS and EXT Trigger bits and regs. */
struct nxp_c45_reg_field pps_enable;
struct nxp_c45_reg_field pps_polarity;
u16 vend1_ext_trg_data_0;
u16 vend1_ext_trg_data_1;
u16 vend1_ext_trg_data_2;
u16 vend1_ext_trg_data_3;
u16 vend1_ext_trg_ctrl;
/* Cable test reg fields. */
u16 cable_test;
struct nxp_c45_reg_field cable_test_valid;
struct nxp_c45_reg_field cable_test_result;
};
struct nxp_c45_phy_stats {
const char *name;
const struct nxp_c45_reg_field counter;
};
struct nxp_c45_phy_data {
const struct nxp_c45_regmap *regmap;
const struct nxp_c45_phy_stats *stats;
int n_stats;
u8 ptp_clk_period;
bool ext_ts_both_edges;
bool ack_ptp_irq;
void (*counters_enable)(struct phy_device *phydev);
bool (*get_egressts)(struct nxp_c45_phy *priv,
struct nxp_c45_hwts *hwts);
bool (*get_extts)(struct nxp_c45_phy *priv, struct timespec64 *extts);
Annotation
- Immediate include surface: `linux/delay.h`, `linux/ethtool.h`, `linux/ethtool_netlink.h`, `linux/kernel.h`, `linux/mii.h`, `linux/module.h`, `linux/of.h`, `linux/phy.h`.
- Detected declarations: `struct nxp_c45_phy`, `struct nxp_c45_skb_cb`, `struct nxp_c45_reg_field`, `struct nxp_c45_hwts`, `struct nxp_c45_regmap`, `struct nxp_c45_phy_stats`, `struct nxp_c45_phy_data`, `function nxp_c45_read_reg_field`, `function nxp_c45_write_reg_field`, `function nxp_c45_set_reg_field`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.