drivers/net/phy/phy-c45.c
Source file repositories/reference/linux-study-clean/drivers/net/phy/phy-c45.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/phy/phy-c45.c- Extension
.c- Size
- 49778 bytes
- Lines
- 1843
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/ethtool.hlinux/export.hlinux/mdio.hlinux/mii.hlinux/phy.hlinux/ethtool_netlink.hmdio-open-alliance.hphylib-internal.h
Detected Declarations
function genphy_c45_baset1_ablefunction genphy_c45_pma_can_sleepfunction genphy_c45_pma_resumefunction genphy_c45_pma_suspendfunction genphy_c45_pma_baset1_setup_master_slavefunction genphy_c45_pma_setup_forcedfunction BITfunction genphy_c45_an_config_anegfunction genphy_c45_an_disable_anegfunction genphy_c45_restart_anegfunction genphy_c45_check_and_restart_anegfunction genphy_c45_aneg_donefunction genphy_c45_read_linkfunction genphy_c45_baset1_read_lpafunction basefunction genphy_c45_pma_baset1_read_master_slavefunction genphy_c45_read_pmafunction genphy_c45_read_mdixfunction genphy_c45_write_eee_advfunction genphy_c45_read_eee_advfunction genphy_c45_read_eee_lpafunction genphy_c45_read_eee_cap1function genphy_c45_read_eee_cap2function genphy_c45_read_eee_abilitiesfunction genphy_c45_an_config_eee_anegfunction genphy_c45_pma_baset1_read_abilitiesfunction genphy_c45_pma_read_ext_abilitiesfunction Abilitiesfunction BITfunction genphy_c45_read_statusfunction genphy_c45_config_anegfunction gen10g_config_anegfunction genphy_c45_loopbackfunction genphy_c45_fast_retrainfunction genphy_c45_plca_get_cfgfunction genphy_c45_plca_set_cfgfunction genphy_c45_plca_get_statusfunction genphy_c45_eee_is_activefunction genphy_c45_ethtool_get_eeefunction genphy_c45_ethtool_set_eeefunction oatc14_cable_test_get_result_codefunction ethnl_cable_test_resultfunction Diagnosticsfunction MSBsfunction Indicatorfunction genphy_c45_oatc14_get_sqiexport genphy_c45_pma_resumeexport genphy_c45_pma_suspend
Annotated Snippet
if (val & MDIO_AN_CTRL1_RESTART) {
phydev->link = 0;
return 0;
}
}
while (mmd_mask && link) {
devad = __ffs(mmd_mask);
mmd_mask &= ~BIT(devad);
/* The link state is latched low so that momentary link
* drops can be detected. Do not double-read the status
* in polling mode to detect such short link drops except
* the link was already down.
*/
if (!phy_polling_mode(phydev) || !phydev->link) {
val = phy_read_mmd(phydev, devad, MDIO_STAT1);
if (val < 0)
return val;
else if (val & MDIO_STAT1_LSTATUS)
continue;
}
val = phy_read_mmd(phydev, devad, MDIO_STAT1);
if (val < 0)
return val;
if (!(val & MDIO_STAT1_LSTATUS))
link = false;
}
phydev->link = link;
return 0;
}
EXPORT_SYMBOL_GPL(genphy_c45_read_link);
/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
* if autoneg is complete. If so read the BASE-T1 Autonegotiation
* Advertisement registers filling in the link partner advertisement,
* pause and asym_pause members in phydev.
*/
static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
{
int val;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
if (val < 0)
return val;
if (!(val & MDIO_AN_STAT1_COMPLETE)) {
linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
phydev->pause = false;
phydev->asym_pause = false;
return 0;
}
linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
if (val < 0)
return val;
mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP;
phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
if (val < 0)
return val;
mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
return 0;
}
/**
* genphy_c45_read_lpa - read the link partner advertisement and pause
* @phydev: target phy_device struct
*
* Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
* filling in the link partner advertisement, pause and asym_pause members
* in @phydev. This assumes that the auto-negotiation MMD is present, and
* the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
* to fill in the remainder of the link partner advert from vendor registers.
*/
Annotation
- Immediate include surface: `linux/ethtool.h`, `linux/export.h`, `linux/mdio.h`, `linux/mii.h`, `linux/phy.h`, `linux/ethtool_netlink.h`, `mdio-open-alliance.h`, `phylib-internal.h`.
- Detected declarations: `function genphy_c45_baset1_able`, `function genphy_c45_pma_can_sleep`, `function genphy_c45_pma_resume`, `function genphy_c45_pma_suspend`, `function genphy_c45_pma_baset1_setup_master_slave`, `function genphy_c45_pma_setup_forced`, `function BIT`, `function genphy_c45_an_config_aneg`, `function genphy_c45_an_disable_aneg`, `function genphy_c45_restart_aneg`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.