drivers/net/pse-pd/pse_regulator.c
Source file repositories/reference/linux-study-clean/drivers/net/pse-pd/pse_regulator.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/pse-pd/pse_regulator.c- Extension
.c- Size
- 3655 bytes
- Lines
- 156
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/of.hlinux/platform_device.hlinux/pse-pd/pse.hlinux/regulator/consumer.h
Detected Declarations
struct pse_reg_privfunction pse_reg_pi_enablefunction pse_reg_pi_disablefunction pse_reg_pi_get_admin_statefunction pse_reg_pi_get_pw_statusfunction pse_reg_probe
Annotated Snippet
struct pse_reg_priv {
struct pse_controller_dev pcdev;
struct regulator *ps; /*power source */
enum ethtool_podl_pse_admin_state admin_state;
};
static struct pse_reg_priv *to_pse_reg(struct pse_controller_dev *pcdev)
{
return container_of(pcdev, struct pse_reg_priv, pcdev);
}
static int
pse_reg_pi_enable(struct pse_controller_dev *pcdev, int id)
{
struct pse_reg_priv *priv = to_pse_reg(pcdev);
int ret;
ret = regulator_enable(priv->ps);
if (ret)
return ret;
priv->admin_state = ETHTOOL_PODL_PSE_ADMIN_STATE_ENABLED;
return 0;
}
static int
pse_reg_pi_disable(struct pse_controller_dev *pcdev, int id)
{
struct pse_reg_priv *priv = to_pse_reg(pcdev);
int ret;
ret = regulator_disable(priv->ps);
if (ret)
return ret;
priv->admin_state = ETHTOOL_PODL_PSE_ADMIN_STATE_DISABLED;
return 0;
}
static int
pse_reg_pi_get_admin_state(struct pse_controller_dev *pcdev, int id,
struct pse_admin_state *admin_state)
{
struct pse_reg_priv *priv = to_pse_reg(pcdev);
admin_state->podl_admin_state = priv->admin_state;
return 0;
}
static int
pse_reg_pi_get_pw_status(struct pse_controller_dev *pcdev, int id,
struct pse_pw_status *pw_status)
{
struct pse_reg_priv *priv = to_pse_reg(pcdev);
int ret;
ret = regulator_is_enabled(priv->ps);
if (ret < 0)
return ret;
if (!ret)
pw_status->podl_pw_status =
ETHTOOL_PODL_PSE_PW_D_STATUS_DISABLED;
else
pw_status->podl_pw_status =
ETHTOOL_PODL_PSE_PW_D_STATUS_DELIVERING;
return 0;
}
static const struct pse_controller_ops pse_reg_ops = {
.pi_get_admin_state = pse_reg_pi_get_admin_state,
.pi_get_pw_status = pse_reg_pi_get_pw_status,
.pi_enable = pse_reg_pi_enable,
.pi_disable = pse_reg_pi_disable,
};
static int
pse_reg_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pse_reg_priv *priv;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (!pdev->dev.of_node)
Annotation
- Immediate include surface: `linux/module.h`, `linux/of.h`, `linux/platform_device.h`, `linux/pse-pd/pse.h`, `linux/regulator/consumer.h`.
- Detected declarations: `struct pse_reg_priv`, `function pse_reg_pi_enable`, `function pse_reg_pi_disable`, `function pse_reg_pi_get_admin_state`, `function pse_reg_pi_get_pw_status`, `function pse_reg_probe`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.