drivers/net/usb/smsc95xx.h

Source file repositories/reference/linux-study-clean/drivers/net/usb/smsc95xx.h

File Facts

System
Linux kernel
Corpus path
drivers/net/usb/smsc95xx.h
Extension
.h
Size
14687 bytes
Lines
353
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SMSC95XX_H
#define _SMSC95XX_H

/* Tx command words */
#define TX_CMD_A_DATA_OFFSET_	(0x001F0000)	/* Data Start Offset */
#define TX_CMD_A_FIRST_SEG_	(0x00002000)	/* First Segment */
#define TX_CMD_A_LAST_SEG_	(0x00001000)	/* Last Segment */
#define TX_CMD_A_BUF_SIZE_	(0x000007FF)	/* Buffer Size */

#define TX_CMD_B_CSUM_ENABLE	(0x00004000)	/* TX Checksum Enable */
#define TX_CMD_B_ADD_CRC_DIS_	(0x00002000)	/* Add CRC Disable */
#define TX_CMD_B_DIS_PADDING_	(0x00001000)	/* Disable Frame Padding */
#define TX_CMD_B_FRAME_LENGTH_	(0x000007FF)	/* Frame Length (bytes) */

/* Rx status word */
#define RX_STS_FF_		(0x40000000)	/* Filter Fail */
#define RX_STS_FL_		(0x3FFF0000)	/* Frame Length */
#define RX_STS_ES_		(0x00008000)	/* Error Summary */
#define RX_STS_BF_		(0x00002000)	/* Broadcast Frame */
#define RX_STS_LE_		(0x00001000)	/* Length Error */
#define RX_STS_RF_		(0x00000800)	/* Runt Frame */
#define RX_STS_MF_		(0x00000400)	/* Multicast Frame */
#define RX_STS_TL_		(0x00000080)	/* Frame too long */
#define RX_STS_CS_		(0x00000040)	/* Collision Seen */
#define RX_STS_FT_		(0x00000020)	/* Frame Type */
#define RX_STS_RW_		(0x00000010)	/* Receive Watchdog */
#define RX_STS_ME_		(0x00000008)	/* MII Error */
#define RX_STS_DB_		(0x00000004)	/* Dribbling */
#define RX_STS_CRC_		(0x00000002)	/* CRC Error */

/* SCSRs - System Control and Status Registers */
/* Device ID and Revision Register */
#define ID_REV			(0x00)
#define ID_REV_CHIP_ID_MASK_	(0xFFFF0000)
#define ID_REV_CHIP_REV_MASK_	(0x0000FFFF)
#define ID_REV_CHIP_ID_9500_	(0x9500)
#define ID_REV_CHIP_ID_9500A_	(0x9E00)
#define ID_REV_CHIP_ID_9512_	(0xEC00)
#define ID_REV_CHIP_ID_9530_	(0x9530)
#define ID_REV_CHIP_ID_89530_	(0x9E08)
#define ID_REV_CHIP_ID_9730_	(0x9730)

/* Interrupt Status Register */
#define INT_STS			(0x08)
#define INT_STS_MAC_RTO_	(0x00040000)	/* MAC Reset Time Out */
#define INT_STS_TX_STOP_	(0x00020000)	/* TX Stopped */
#define INT_STS_RX_STOP_	(0x00010000)	/* RX Stopped */
#define INT_STS_PHY_INT_	(0x00008000)	/* PHY Interrupt */
#define INT_STS_TXE_		(0x00004000)	/* Transmitter Error */
#define INT_STS_TDFU_		(0x00002000)	/* TX Data FIFO Underrun */
#define INT_STS_TDFO_		(0x00001000)	/* TX Data FIFO Overrun */
#define INT_STS_RXDF_		(0x00000800)	/* RX Dropped Frame */
#define INT_STS_GPIOS_		(0x000007FF)	/* GPIOs Interrupts */
#define INT_STS_CLEAR_ALL_	(0xFFFFFFFF)

/* Receive Configuration Register */
#define RX_CFG			(0x0C)
#define RX_FIFO_FLUSH_		(0x00000001)	/* Receive FIFO Flush */

/* Transmit Configuration Register */
#define TX_CFG			(0x10)
#define TX_CFG_ON_		(0x00000004)	/* Transmitter Enable */
#define TX_CFG_STOP_		(0x00000002)	/* Stop Transmitter */
#define TX_CFG_FIFO_FLUSH_	(0x00000001)	/* Transmit FIFO Flush */

/* Hardware Configuration Register */
#define HW_CFG			(0x14)
#define HW_CFG_BIR_		(0x00001000)	/* Bulk In Empty Response */
#define HW_CFG_LEDB_		(0x00000800)	/* Activity LED 80ms Bypass */
#define HW_CFG_RXDOFF_		(0x00000600)	/* RX Data Offset */
#define HW_CFG_SBP_		(0x00000100)	/* Stall Bulk Out Pipe Dis. */
#define HW_CFG_IME_		(0x00000080)	/* Internal MII Visi. Enable */
#define HW_CFG_DRP_		(0x00000040)	/* Discard Errored RX Frame */
#define HW_CFG_MEF_		(0x00000020)	/* Mult. ETH Frames/USB pkt */
#define HW_CFG_ETC_		(0x00000010)	/* EEPROM Timeout Control */
#define HW_CFG_LRST_		(0x00000008)	/* Soft Lite Reset */
#define HW_CFG_PSEL_		(0x00000004)	/* External PHY Select */
#define HW_CFG_BCE_		(0x00000002)	/* Burst Cap Enable */
#define HW_CFG_SRST_		(0x00000001)	/* Soft Reset */

/* Receive FIFO Information Register */
#define RX_FIFO_INF		(0x18)
#define RX_FIFO_INF_USED_	(0x0000FFFF)	/* RX Data FIFO Used Space */

/* Transmit FIFO Information Register */
#define TX_FIFO_INF		(0x1C)
#define TX_FIFO_INF_FREE_	(0x0000FFFF)	/* TX Data FIFO Free Space */

/* Power Management Control Register */
#define PM_CTRL			(0x20)

Annotation

Implementation Notes