drivers/net/wan/framer/pef2256/pef2256-regs.h

Source file repositories/reference/linux-study-clean/drivers/net/wan/framer/pef2256/pef2256-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wan/framer/pef2256/pef2256-regs.h
Extension
.h
Size
9809 bytes
Lines
251
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __PEF2256_REGS_H__
#define __PEF2256_REGS_H__

#include "linux/bitfield.h"

/* Command Register */
#define PEF2256_CMDR		0x02
#define PEF2256_CMDR_RRES	BIT(6)
#define PEF2256_CMDR_XRES	BIT(4)
#define PEF2256_CMDR_SRES	BIT(0)

/* Interrupt Mask Register 0..5 */
#define PEF2256_IMR0	        0x14
#define PEF2256_IMR1	        0x15
#define PEF2256_IMR2	        0x16
#define PEF2256_IMR3	        0x17
#define PEF2256_IMR4	        0x18
#define PEF2256_IMR5	        0x19

/* Framer Mode Register 0 */
#define PEF2256_FMR0		0x1C
#define PEF2256_FMR0_XC_MASK	GENMASK(7, 6)
#define PEF2256_FMR0_XC_NRZ	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)
#define PEF2256_FMR0_XC_CMI	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)
#define PEF2256_FMR0_XC_AMI	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)
#define PEF2256_FMR0_XC_HDB3	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
#define PEF2256_FMR0_RC_MASK	GENMASK(5, 4)
#define PEF2256_FMR0_RC_NRZ	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)
#define PEF2256_FMR0_RC_CMI	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)
#define PEF2256_FMR0_RC_AMI	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)
#define PEF2256_FMR0_RC_HDB3	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)

/* Framer Mode Register 1 */
#define PEF2256_FMR1		0x1D
#define PEF2256_FMR1_XFS	BIT(3)
#define PEF2256_FMR1_ECM	BIT(2)
/* SSD is defined on 2 bits. The other bit is on SIC1 register */
#define PEF2256_FMR1_SSD_MASK	GENMASK(1, 1)
#define PEF2256_FMR1_SSD_2048	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
#define PEF2256_FMR1_SSD_4096	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
#define PEF2256_FMR1_SSD_8192	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
#define PEF2256_FMR1_SSD_16384	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)

/* Framer Mode Register 2 */
#define PEF2256_FMR2			  0x1E
#define PEF2256_FMR2_RFS_MASK		  GENMASK(7, 6)
#define PEF2256_FMR2_RFS_DOUBLEFRAME	  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x0)
#define PEF2256_FMR2_RFS_CRC4_MULTIFRAME  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x2)
#define PEF2256_FMR2_RFS_AUTO_MULTIFRAME  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3)
#define PEF2256_FMR2_AXRA		  BIT(1)

/* Transmit Service Word */
#define PEF2256_XSW		0x20
#define PEF2256_XSW_XSIS	BIT(7)
#define PEF2256_XSW_XTM		BIT(6)
#define PEF2256_XSW_XY_MASK	GENMASK(5, 0)
#define PEF2256_XSW_XY(_v)	FIELD_PREP(PEF2256_XSW_XY_MASK, _v)

/* Transmit Spare Bits */
#define PEF2256_XSP	        0x21
#define PEF2256_XSP_XSIF	BIT(2)

/* Transmit Control 0..1 */
#define PEF2256_XC0		0x22
#define PEF2256_XC1		0x23

/* Receive Control 0 */
#define PEF2256_RC0		0x24
#define PEF2256_RC0_SWD		BIT(7)
#define PEF2256_RC0_ASY4	BIT(6)

/* Receive Control 1 */
#define PEF2256_RC1		0x25

/* Transmit Pulse Mask 0..1 */
#define PEF2256_XPM0		0x26
#define PEF2256_XPM1		0x27

/* Transmit Pulse Mask 2 */
#define PEF2256_XPM2		0x28
#define PEF2256_XPM2_XLT	BIT(6)

/* Transparent Service Word Mask */
#define PEF2256_TSWM		0x29

/* Line Interface Mode 0 */
#define PEF2256_LIM0		0x36
#define PEF2256_2X_LIM0_BIT3	BIT(3) /* v2.x, described as a forced '1' bit */
#define PEF2256_LIM0_MAS	BIT(0)

Annotation

Implementation Notes