drivers/net/wan/hd64570.h

Source file repositories/reference/linux-study-clean/drivers/net/wan/hd64570.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wan/hd64570.h
Extension
.h
Size
8690 bytes
Lines
243
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __HD64570_H
#define __HD64570_H

/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
   and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.

   Source: HD64570 SCA User's Manual
*/



/* SCA Control Registers */
#define LPR    0x00		/* Low Power */

/* Wait controller registers */
#define PABR0  0x02		/* Physical Address Boundary 0 */
#define PABR1  0x03		/* Physical Address Boundary 1 */
#define WCRL   0x04		/* Wait Control L */
#define WCRM   0x05		/* Wait Control M */
#define WCRH   0x06		/* Wait Control H */

#define PCR    0x08		/* DMA Priority Control */
#define DMER   0x09		/* DMA Master Enable */


/* Interrupt registers */
#define ISR0   0x10		/* Interrupt Status 0  */
#define ISR1   0x11		/* Interrupt Status 1  */
#define ISR2   0x12		/* Interrupt Status 2  */

#define IER0   0x14		/* Interrupt Enable 0  */
#define IER1   0x15		/* Interrupt Enable 1  */
#define IER2   0x16		/* Interrupt Enable 2  */

#define ITCR   0x18		/* Interrupt Control */
#define IVR    0x1A		/* Interrupt Vector */
#define IMVR   0x1C		/* Interrupt Modified Vector */



/* MSCI channel (port) 0 registers - offset 0x20
   MSCI channel (port) 1 registers - offset 0x40 */

#define MSCI0_OFFSET 0x20
#define MSCI1_OFFSET 0x40

#define TRBL   0x00		/* TX/RX buffer L */ 
#define TRBH   0x01		/* TX/RX buffer H */ 
#define ST0    0x02		/* Status 0 */
#define ST1    0x03		/* Status 1 */
#define ST2    0x04		/* Status 2 */
#define ST3    0x05		/* Status 3 */
#define FST    0x06		/* Frame Status  */
#define IE0    0x08		/* Interrupt Enable 0 */
#define IE1    0x09		/* Interrupt Enable 1 */
#define IE2    0x0A		/* Interrupt Enable 2 */
#define FIE    0x0B		/* Frame Interrupt Enable  */
#define CMD    0x0C		/* Command */
#define MD0    0x0E		/* Mode 0 */
#define MD1    0x0F		/* Mode 1 */
#define MD2    0x10		/* Mode 2 */
#define CTL    0x11		/* Control */
#define SA0    0x12		/* Sync/Address 0 */
#define SA1    0x13		/* Sync/Address 1 */
#define IDL    0x14		/* Idle Pattern */
#define TMC    0x15		/* Time Constant */
#define RXS    0x16		/* RX Clock Source */
#define TXS    0x17		/* TX Clock Source */
#define TRC0   0x18		/* TX Ready Control 0 */ 
#define TRC1   0x19		/* TX Ready Control 1 */ 
#define RRC    0x1A		/* RX Ready Control */ 
#define CST0   0x1C		/* Current Status 0 */
#define CST1   0x1D		/* Current Status 1 */


/* Timer channel 0 (port 0 RX) registers - offset 0x60
   Timer channel 1 (port 0 TX) registers - offset 0x68
   Timer channel 2 (port 1 RX) registers - offset 0x70
   Timer channel 3 (port 1 TX) registers - offset 0x78
*/

#define TIMER0RX_OFFSET 0x60
#define TIMER0TX_OFFSET 0x68
#define TIMER1RX_OFFSET 0x70
#define TIMER1TX_OFFSET 0x78

#define TCNTL  0x00		/* Up-counter L */
#define TCNTH  0x01		/* Up-counter H */
#define TCONRL 0x02		/* Constant L */
#define TCONRH 0x03		/* Constant H */

Annotation

Implementation Notes