drivers/net/wan/hd64572.h

Source file repositories/reference/linux-study-clean/drivers/net/wan/hd64572.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wan/hd64572.h
Extension
.h
Size
15862 bytes
Lines
523
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __HD64572_H
#define __HD64572_H

/* Illegal Access Register */
#define	ILAR	0x00

/* Wait Controller Registers */
#define PABR0L	0x20	/* Physical Addr Boundary Register 0 L */
#define PABR0H	0x21	/* Physical Addr Boundary Register 0 H */
#define PABR1L	0x22	/* Physical Addr Boundary Register 1 L */
#define PABR1H	0x23	/* Physical Addr Boundary Register 1 H */
#define WCRL	0x24	/* Wait Control Register L */
#define WCRM	0x25	/* Wait Control Register M */
#define WCRH	0x26	/* Wait Control Register H */

/* Interrupt Registers */
#define IVR	0x60	/* Interrupt Vector Register */
#define IMVR	0x64	/* Interrupt Modified Vector Register */
#define ITCR	0x68	/* Interrupt Control Register */
#define ISR0	0x6c	/* Interrupt Status Register 0 */
#define ISR1	0x70	/* Interrupt Status Register 1 */
#define IER0	0x74	/* Interrupt Enable Register 0 */
#define IER1	0x78	/* Interrupt Enable Register 1 */

/* Register Access Macros (chan is 0 or 1 in _any_ case) */
#define	M_REG(reg, chan)	(reg + 0x80*chan)		/* MSCI */
#define	DRX_REG(reg, chan)	(reg + 0x40*chan)		/* DMA Rx */
#define	DTX_REG(reg, chan)	(reg + 0x20*(2*chan + 1))	/* DMA Tx */
#define	TRX_REG(reg, chan)	(reg + 0x20*chan)		/* Timer Rx */
#define	TTX_REG(reg, chan)	(reg + 0x10*(2*chan + 1))	/* Timer Tx */
#define	ST_REG(reg, chan)	(reg + 0x80*chan)		/* Status Cnt */
#define IR0_DRX(val, chan)	((val)<<(8*(chan)))		/* Int DMA Rx */
#define IR0_DTX(val, chan)	((val)<<(4*(2*chan + 1)))	/* Int DMA Tx */
#define IR0_M(val, chan)	((val)<<(8*(chan)))		/* Int MSCI */

/* MSCI Channel Registers */
#define MSCI0_OFFSET 0x00
#define MSCI1_OFFSET 0x80

#define MD0	0x138	/* Mode reg 0 */
#define MD1	0x139	/* Mode reg 1 */
#define MD2	0x13a	/* Mode reg 2 */
#define MD3	0x13b	/* Mode reg 3 */
#define CTL	0x130	/* Control reg */
#define RXS	0x13c	/* RX clock source */
#define TXS	0x13d	/* TX clock source */
#define EXS	0x13e	/* External clock input selection */
#define TMCT	0x144	/* Time constant (Tx) */
#define TMCR	0x145	/* Time constant (Rx) */
#define CMD	0x128	/* Command reg */
#define ST0	0x118	/* Status reg 0 */
#define ST1	0x119	/* Status reg 1 */
#define ST2	0x11a	/* Status reg 2 */
#define ST3	0x11b	/* Status reg 3 */
#define ST4	0x11c	/* Status reg 4 */
#define FST	0x11d	/* frame Status reg  */
#define IE0	0x120	/* Interrupt enable reg 0 */
#define IE1	0x121	/* Interrupt enable reg 1 */
#define IE2	0x122	/* Interrupt enable reg 2 */
#define IE4	0x124	/* Interrupt enable reg 4 */
#define FIE	0x125	/* Frame Interrupt enable reg  */
#define SA0	0x140	/* Syn Address reg 0 */
#define SA1	0x141	/* Syn Address reg 1 */
#define IDL	0x142	/* Idle register */
#define TRBL	0x100	/* TX/RX buffer reg L */ 
#define TRBK	0x101	/* TX/RX buffer reg K */ 
#define TRBJ	0x102	/* TX/RX buffer reg J */ 
#define TRBH	0x103	/* TX/RX buffer reg H */ 
#define TRC0	0x148	/* TX Ready control reg 0 */ 
#define TRC1	0x149	/* TX Ready control reg 1 */ 
#define RRC	0x14a	/* RX Ready control reg */ 
#define CST0	0x108	/* Current Status Register 0 */ 
#define CST1	0x109	/* Current Status Register 1 */ 
#define CST2	0x10a	/* Current Status Register 2 */ 
#define CST3	0x10b	/* Current Status Register 3 */ 
#define GPO	0x131	/* General Purpose Output Pin Ctl Reg */
#define TFS	0x14b	/* Tx Start Threshold Ctl Reg */
#define TFN	0x143	/* Inter-transmit-frame Time Fill Ctl Reg */
#define TBN	0x110	/* Tx Buffer Number Reg */
#define RBN	0x111	/* Rx Buffer Number Reg */
#define TNR0	0x150	/* Tx DMA Request Ctl Reg 0 */
#define TNR1	0x151	/* Tx DMA Request Ctl Reg 1 */
#define TCR	0x152	/* Tx DMA Critical Request Reg */
#define RNR	0x154	/* Rx DMA Request Ctl Reg */
#define RCR	0x156	/* Rx DMA Critical Request Reg */

/* Timer Registers */
#define TIMER0RX_OFFSET 0x00
#define TIMER0TX_OFFSET 0x10
#define TIMER1RX_OFFSET 0x20

Annotation

Implementation Notes