drivers/net/wan/slic_ds26522.h

File Facts

System

Linux kernel

Corpus path

drivers/net/wan/slic_ds26522.h

Extension

.h

Size

3284 bytes

Lines

131

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• enum line_rate
• enum tdm_trans_mode
• enum card_support_type

Annotated Snippet

#define DS26522_RF_ADDR_START	0x00
#define DS26522_RF_ADDR_END	0xef
#define DS26522_GLB_ADDR_START	0xf0
#define DS26522_GLB_ADDR_END	0xff
#define DS26522_TF_ADDR_START	0x100
#define DS26522_TF_ADDR_END	0x1ef
#define DS26522_LIU_ADDR_START	0x1000
#define DS26522_LIU_ADDR_END	0x101f
#define DS26522_TEST_ADDR_START	0x1008
#define DS26522_TEST_ADDR_END	0x101f
#define DS26522_BERT_ADDR_START	0x1100
#define DS26522_BERT_ADDR_END	0x110f

#define DS26522_RMMR_ADDR	0x80
#define DS26522_RCR1_ADDR	0x81
#define DS26522_RCR3_ADDR	0x83
#define DS26522_RIOCR_ADDR	0x84

#define DS26522_GTCR1_ADDR	0xf0
#define DS26522_GFCR_ADDR	0xf1
#define DS26522_GTCR2_ADDR	0xf2
#define DS26522_GTCCR_ADDR	0xf3
#define DS26522_GLSRR_ADDR	0xf5
#define DS26522_GFSRR_ADDR	0xf6
#define DS26522_IDR_ADDR	0xf8

#define DS26522_E1TAF_ADDR	0x164
#define DS26522_E1TNAF_ADDR	0x165
#define DS26522_TMMR_ADDR	0x180
#define DS26522_TCR1_ADDR	0x181
#define DS26522_TIOCR_ADDR	0x184

#define DS26522_LTRCR_ADDR	0x1000
#define DS26522_LTITSR_ADDR	0x1001
#define DS26522_LMCR_ADDR	0x1002
#define DS26522_LRISMR_ADDR	0x1007

#define MAX_NUM_OF_CHANNELS	8
#define PQ_MDS_8E1T1_BRD_REV	0x00
#define PQ_MDS_8E1T1_PLD_REV	0x00

#define DS26522_GTCCR_BPREFSEL_REFCLKIN	0xa0
#define DS26522_GTCCR_BFREQSEL_1544KHZ	0x08
#define DS26522_GTCCR_FREQSEL_1544KHZ	0x04
#define DS26522_GTCCR_BFREQSEL_2048KHZ	0x00
#define DS26522_GTCCR_FREQSEL_2048KHZ	0x00

#define DS26522_GFCR_BPCLK_2048KHZ	0x00

#define DS26522_GTCR2_TSSYNCOUT	0x02
#define DS26522_GTCR1	0x00

#define DS26522_GFSRR_RESET	0x01
#define DS26522_GFSRR_NORMAL	0x00

#define DS26522_GLSRR_RESET	0x01
#define DS26522_GLSRR_NORMAL	0x00

#define DS26522_RMMR_SFTRST	0x02
#define DS26522_RMMR_FRM_EN	0x80
#define DS26522_RMMR_INIT_DONE	0x40
#define DS26522_RMMR_T1		0x00
#define DS26522_RMMR_E1		0x01

#define DS26522_E1TAF_DEFAULT	0x1b
#define DS26522_E1TNAF_DEFAULT	0x40

#define DS26522_TMMR_SFTRST	0x02
#define DS26522_TMMR_FRM_EN	0x80
#define DS26522_TMMR_INIT_DONE	0x40
#define DS26522_TMMR_T1		0x00
#define DS26522_TMMR_E1		0x01

#define DS26522_RCR1_T1_SYNCT	0x80
#define DS26522_RCR1_T1_RB8ZS	0x40
#define DS26522_RCR1_T1_SYNCC	0x08

#define DS26522_RCR1_E1_HDB3	0x40
#define DS26522_RCR1_E1_CCS	0x20

#define DS26522_RIOCR_1544KHZ	0x00
#define DS26522_RIOCR_2048KHZ	0x10
#define DS26522_RIOCR_RSIO_OUT	0x00

#define DS26522_RCR3_FLB	0x01

#define DS26522_TIOCR_1544KHZ	0x00
#define DS26522_TIOCR_2048KHZ	0x10
#define DS26522_TIOCR_TSIO_OUT	0x04

Annotation

• Detected declarations: `enum line_rate`, `enum tdm_trans_mode`, `enum card_support_type`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.