drivers/net/wireless/ath/ath10k/qmi.h
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath10k/qmi.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath10k/qmi.h- Extension
.h- Size
- 2759 bytes
- Lines
- 124
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/soc/qcom/qmi.hlinux/qrtr.hqmi_wlfw_v01.h
Detected Declarations
struct ath10k_msa_mem_infostruct ath10k_qmi_chip_infostruct ath10k_qmi_board_infostruct ath10k_qmi_soc_infostruct ath10k_qmi_cal_datastruct ath10k_tgt_pipe_cfgstruct ath10k_svc_pipe_cfgstruct ath10k_shadow_reg_cfgstruct ath10k_qmi_wlan_enable_cfgstruct ath10k_qmi_driver_eventstruct ath10k_qmienum ath10k_qmi_driver_event_typeenum ath10k_qmi_state
Annotated Snippet
struct ath10k_msa_mem_info {
phys_addr_t addr;
u32 size;
bool secure;
};
struct ath10k_qmi_chip_info {
u32 chip_id;
u32 chip_family;
};
struct ath10k_qmi_board_info {
u32 board_id;
};
struct ath10k_qmi_soc_info {
u32 soc_id;
};
struct ath10k_qmi_cal_data {
u32 cal_id;
u32 total_size;
u8 *data;
};
struct ath10k_tgt_pipe_cfg {
__le32 pipe_num;
__le32 pipe_dir;
__le32 nentries;
__le32 nbytes_max;
__le32 flags;
__le32 reserved;
};
struct ath10k_svc_pipe_cfg {
__le32 service_id;
__le32 pipe_dir;
__le32 pipe_num;
};
struct ath10k_shadow_reg_cfg {
__le16 ce_id;
__le16 reg_offset;
};
struct ath10k_qmi_wlan_enable_cfg {
u32 num_ce_tgt_cfg;
struct ath10k_tgt_pipe_cfg *ce_tgt_cfg;
u32 num_ce_svc_pipe_cfg;
struct ath10k_svc_pipe_cfg *ce_svc_cfg;
u32 num_shadow_reg_cfg;
struct ath10k_shadow_reg_cfg *shadow_reg_cfg;
};
struct ath10k_qmi_driver_event {
struct list_head list;
enum ath10k_qmi_driver_event_type type;
void *data;
};
enum ath10k_qmi_state {
ATH10K_QMI_STATE_INIT_DONE,
ATH10K_QMI_STATE_DEINIT,
};
struct ath10k_qmi {
struct ath10k *ar;
struct qmi_handle qmi_hdl;
struct sockaddr_qrtr sq;
struct work_struct event_work;
struct workqueue_struct *event_wq;
struct list_head event_list;
spinlock_t event_lock; /* spinlock for qmi event list */
u32 nr_mem_region;
struct ath10k_msa_mem_info mem_region[MAX_NUM_MEMORY_REGIONS];
struct ath10k_qmi_chip_info chip_info;
struct ath10k_qmi_board_info board_info;
struct ath10k_qmi_soc_info soc_info;
char fw_build_id[MAX_BUILD_ID_LEN + 1];
u32 fw_version;
bool fw_ready;
char fw_build_timestamp[MAX_TIMESTAMP_LEN + 1];
struct ath10k_qmi_cal_data cal_data[MAX_NUM_CAL_V01];
bool msa_fixed_perm;
bool no_msa_ready_indicator;
enum ath10k_qmi_state state;
};
int ath10k_qmi_wlan_enable(struct ath10k *ar,
struct ath10k_qmi_wlan_enable_cfg *config,
Annotation
- Immediate include surface: `linux/soc/qcom/qmi.h`, `linux/qrtr.h`, `qmi_wlfw_v01.h`.
- Detected declarations: `struct ath10k_msa_mem_info`, `struct ath10k_qmi_chip_info`, `struct ath10k_qmi_board_info`, `struct ath10k_qmi_soc_info`, `struct ath10k_qmi_cal_data`, `struct ath10k_tgt_pipe_cfg`, `struct ath10k_svc_pipe_cfg`, `struct ath10k_shadow_reg_cfg`, `struct ath10k_qmi_wlan_enable_cfg`, `struct ath10k_qmi_driver_event`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.