drivers/net/wireless/ath/ath11k/hal.h
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath11k/hal.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath11k/hal.h- Extension
.h- Size
- 33006 bytes
- Lines
- 979
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hal_desc.hrx_desc.h
Detected Declarations
struct ath11k_basestruct hal_wbm_idle_scatter_liststruct hal_srng_paramsstruct hal_srngstruct hal_srng_configstruct ath11k_hal_reo_cmdstruct hal_reo_status_headerstruct hal_reo_status_queue_statsstruct hal_reo_status_flush_queuestruct hal_reo_status_flush_cachestruct hal_reo_status_unblock_cachestruct hal_reo_status_flush_timeout_liststruct hal_reo_status_desc_thresh_reachedstruct hal_reo_statusstruct ath11k_halenum hal_srng_ring_idenum hal_ring_typeenum hal_reo_cmd_typeenum hal_reo_cmd_statusenum hal_srng_direnum hal_rx_buf_return_buf_managerenum hal_pn_typeenum hal_ce_descenum hal_reo_status_flush_cache_err_codeenum hal_reo_status_unblock_cache_typeenum hal_reo_threshold_idx
Annotated Snippet
struct hal_wbm_idle_scatter_list {
dma_addr_t paddr;
struct hal_wbm_link_desc *vaddr;
};
struct hal_srng_params {
dma_addr_t ring_base_paddr;
u32 *ring_base_vaddr;
int num_entries;
u32 intr_batch_cntr_thres_entries;
u32 intr_timer_thres_us;
u32 flags;
u32 max_buffer_len;
u32 low_threshold;
dma_addr_t msi_addr;
u32 msi_data;
/* Add more params as needed */
};
enum hal_srng_dir {
HAL_SRNG_DIR_SRC,
HAL_SRNG_DIR_DST
};
/* srng flags */
#define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
#define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
#define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
#define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
#define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
#define HAL_SRNG_FLAGS_CACHED 0x20000000
#define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
#define HAL_SRNG_FLAGS_REMAP_CE_RING 0x10000000
#define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
#define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
/* Common SRNG ring structure for source and destination rings */
struct hal_srng {
/* Unique SRNG ring ID */
u8 ring_id;
/* Ring initialization done */
u8 initialized;
/* Interrupt/MSI value assigned to this ring */
int irq;
/* Physical base address of the ring */
dma_addr_t ring_base_paddr;
/* Virtual base address of the ring */
u32 *ring_base_vaddr;
/* Number of entries in ring */
u32 num_entries;
/* Ring size */
u32 ring_size;
/* Ring size mask */
u32 ring_size_mask;
/* Size of ring entry */
u32 entry_size;
/* Interrupt timer threshold - in micro seconds */
u32 intr_timer_thres_us;
/* Interrupt batch counter threshold - in number of ring entries */
u32 intr_batch_cntr_thres_entries;
/* MSI Address */
dma_addr_t msi_addr;
/* MSI data */
u32 msi_data;
/* Misc flags */
u32 flags;
/* Lock for serializing ring index updates */
spinlock_t lock;
/* Start offset of SRNG register groups for this ring
* TBD: See if this is required - register address can be derived
* from ring ID
*/
u32 hwreg_base[HAL_SRNG_NUM_REG_GRP];
Annotation
- Immediate include surface: `hal_desc.h`, `rx_desc.h`.
- Detected declarations: `struct ath11k_base`, `struct hal_wbm_idle_scatter_list`, `struct hal_srng_params`, `struct hal_srng`, `struct hal_srng_config`, `struct ath11k_hal_reo_cmd`, `struct hal_reo_status_header`, `struct hal_reo_status_queue_stats`, `struct hal_reo_status_flush_queue`, `struct hal_reo_status_flush_cache`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.