drivers/net/wireless/ath/ath12k/hal.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath12k/hal.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath12k/hal.c- Extension
.c- Size
- 23414 bytes
- Lines
- 872
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hdebug.hhif.h
Detected Declarations
function Copyrightfunction ath12k_hal_srng_src_hw_initfunction ath12k_hal_srng_dst_hw_initfunction ath12k_hal_set_umac_srng_ptr_addrfunction ath12k_hal_srng_get_ring_idfunction ath12k_hal_srng_update_shadow_configfunction ath12k_hal_ce_get_desc_sizefunction ath12k_hal_tx_set_dscp_tid_mapfunction ath12k_hal_tx_configure_bank_registerfunction ath12k_hal_reoq_lut_addr_read_enablefunction ath12k_hal_reoq_lut_set_max_peeridfunction ath12k_hal_write_ml_reoq_lut_addrfunction ath12k_hal_write_reoq_lut_addrfunction ath12k_hal_setup_link_idle_listfunction ath12k_hal_reo_hw_setupfunction ath12k_hal_reo_init_cmd_ringfunction ath12k_hal_reo_shared_qaddr_cache_clearfunction ath12k_hal_rx_buf_addr_info_setfunction ath12k_hal_rx_buf_addr_info_getfunction ath12k_hal_rx_msdu_list_getfunction ath12k_hal_rx_reo_ent_buf_paddr_getfunction ath12k_hal_cc_configfunction ath12k_hal_get_idle_link_rbmfunction ath12k_hal_alloc_cont_rdpfunction ath12k_hal_free_cont_rdpfunction ath12k_hal_alloc_cont_wrpfunction ath12k_hal_free_cont_wrpfunction ath12k_hal_srng_hw_initfunction ath12k_hal_srng_get_entrysizefunction ath12k_hal_srng_get_max_entriesfunction ath12k_hal_srng_get_paramsfunction ath12k_hal_srng_get_hp_addrfunction ath12k_hal_srng_get_tp_addrfunction ath12k_hal_ce_src_set_descfunction ath12k_hal_ce_dst_set_descfunction ath12k_hal_ce_dst_status_get_lengthfunction ath12k_hal_set_link_desc_addrfunction ath12k_hal_srng_dst_num_freefunction ath12k_hal_srng_src_num_freefunction ath12k_hal_srng_access_beginfunction ath12k_hal_srng_access_endfunction ath12k_hal_srng_setupfunction ath12k_hal_srng_shadow_configfunction ath12k_hal_srng_get_shadow_configfunction ath12k_hal_srng_shadow_update_hp_tpfunction ath12k_hal_register_srng_lock_keysfunction ath12k_hal_unregister_srng_lock_keysfunction ath12k_hal_srng_init
Annotated Snippet
if (hp != srng->u.dst_ring.cached_hp) {
srng->u.dst_ring.cached_hp = hp;
/* Make sure descriptor is read after the head
* pointer.
*/
dma_rmb();
}
}
}
EXPORT_SYMBOL(ath12k_hal_srng_access_begin);
/* Update cached ring head/tail pointers to HW. ath12k_hal_srng_access_begin()
* should have been called before this.
*/
void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng)
{
lockdep_assert_held(&srng->lock);
if (srng->flags & HAL_SRNG_FLAGS_LMAC_RING) {
/* For LMAC rings, ring pointer updates are done through FW and
* hence written to a shared memory location that is read by FW
*/
if (srng->ring_dir == HAL_SRNG_DIR_SRC) {
srng->u.src_ring.last_tp =
*(volatile u32 *)srng->u.src_ring.tp_addr;
/* Make sure descriptor is written before updating the
* head pointer.
*/
dma_wmb();
WRITE_ONCE(*srng->u.src_ring.hp_addr, srng->u.src_ring.hp);
} else {
srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr;
/* Make sure descriptor is read before updating the
* tail pointer.
*/
dma_mb();
WRITE_ONCE(*srng->u.dst_ring.tp_addr, srng->u.dst_ring.tp);
}
} else {
if (srng->ring_dir == HAL_SRNG_DIR_SRC) {
srng->u.src_ring.last_tp =
*(volatile u32 *)srng->u.src_ring.tp_addr;
/* Assume implementation use an MMIO write accessor
* which has the required wmb() so that the descriptor
* is written before the updating the head pointer.
*/
ath12k_hif_write32(ab,
(unsigned long)srng->u.src_ring.hp_addr -
(unsigned long)ab->mem,
srng->u.src_ring.hp);
} else {
srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr;
/* Make sure descriptor is read before updating the
* tail pointer.
*/
mb();
ath12k_hif_write32(ab,
(unsigned long)srng->u.dst_ring.tp_addr -
(unsigned long)ab->mem,
srng->u.dst_ring.tp);
}
}
srng->timestamp = jiffies;
}
EXPORT_SYMBOL(ath12k_hal_srng_access_end);
int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type,
int ring_num, int mac_id,
struct hal_srng_params *params)
{
struct ath12k_hal *hal = &ab->hal;
struct hal_srng_config *srng_config = &ab->hal.srng_config[type];
struct hal_srng *srng;
int ring_id;
u32 idx;
int i;
ring_id = ath12k_hal_srng_get_ring_id(hal, type, ring_num, mac_id);
if (ring_id < 0)
return ring_id;
srng = &hal->srng_list[ring_id];
srng->ring_id = ring_id;
srng->ring_dir = srng_config->ring_dir;
srng->ring_base_paddr = params->ring_base_paddr;
srng->ring_base_vaddr = params->ring_base_vaddr;
srng->entry_size = srng_config->entry_size;
srng->num_entries = params->num_entries;
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `debug.h`, `hif.h`.
- Detected declarations: `function Copyright`, `function ath12k_hal_srng_src_hw_init`, `function ath12k_hal_srng_dst_hw_init`, `function ath12k_hal_set_umac_srng_ptr_addr`, `function ath12k_hal_srng_get_ring_id`, `function ath12k_hal_srng_update_shadow_config`, `function ath12k_hal_ce_get_desc_size`, `function ath12k_hal_tx_set_dscp_tid_map`, `function ath12k_hal_tx_configure_bank_register`, `function ath12k_hal_reoq_lut_addr_read_enable`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.