drivers/net/wireless/ath/ath12k/wifi7/hal.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath12k/wifi7/hal.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath12k/wifi7/hal.c- Extension
.c- Size
- 23429 bytes
- Lines
- 721
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
hw.hhal_desc.h../hal.hhal.hhal_tx.h../debug.h../hif.hhal_qcn9274.hhal_wcn7850.hhal_qcc2072.h
Detected Declarations
function ath12k_wifi7_hal_initfunction ath12k_wifi7_hal_reo1_ring_id_offsetfunction ath12k_wifi7_hal_reo1_ring_msi1_base_lsb_offsetfunction ath12k_wifi7_hal_reo1_ring_msi1_base_msb_offsetfunction ath12k_wifi7_hal_reo1_ring_msi1_data_offsetfunction ath12k_wifi7_hal_reo1_ring_base_msb_offsetfunction ath12k_wifi7_hal_reo1_ring_producer_int_setup_offsetfunction ath12k_wifi7_hal_reo1_ring_hp_addr_lsb_offsetfunction ath12k_wifi7_hal_reo1_ring_hp_addr_msb_offsetfunction ath12k_wifi7_hal_reo1_ring_misc_offsetfunction ath12k_wifi7_hal_ce_dst_setupfunction ath12k_wifi7_hal_srng_dst_hw_initfunction ath12k_wifi7_hal_srng_src_hw_initfunction ath12k_wifi7_hal_set_umac_srng_ptr_addrfunction ath12k_wifi7_hal_srng_get_ring_idfunction ath12k_wifi7_hal_srng_update_hp_tp_addrfunction ath12k_wifi7_hal_ce_get_desc_sizefunction ath12k_wifi7_hal_srng_update_shadow_configfunction ath12k_wifi7_hal_ce_src_set_descfunction ath12k_wifi7_hal_ce_dst_set_descfunction ath12k_wifi7_hal_set_link_desc_addrfunction ath12k_wifi7_hal_ce_dst_status_get_lengthfunction ath12k_wifi7_hal_setup_link_idle_listfunction ath12k_wifi7_hal_tx_configure_bank_registerfunction ath12k_wifi7_hal_reoq_lut_addr_read_enablefunction ath12k_wifi7_hal_reoq_lut_set_max_peeridfunction ath12k_wifi7_hal_write_reoq_lut_addrfunction ath12k_wifi7_hal_write_ml_reoq_lut_addrfunction ath12k_wifi7_hal_cc_configfunction ath12k_wifi7_hal_get_idle_link_rbm
Annotated Snippet
if (!ab->hw_params->supports_shadow_regs) {
srng->u.src_ring.hp_addr =
(u32 *)((unsigned long)ab->mem + reg_base);
} else {
ath12k_dbg(ab, ATH12K_DBG_HAL,
"hal reg_base 0x%x shadow 0x%lx\n",
reg_base,
(unsigned long)srng->u.src_ring.hp_addr -
(unsigned long)ab->mem);
}
} else {
if (!ab->hw_params->supports_shadow_regs) {
srng->u.dst_ring.tp_addr =
(u32 *)((unsigned long)ab->mem + reg_base +
(HAL_REO1_RING_TP - HAL_REO1_RING_HP));
} else {
ath12k_dbg(ab, ATH12K_DBG_HAL,
"target_reg 0x%x shadow 0x%lx\n",
reg_base + HAL_REO1_RING_TP - HAL_REO1_RING_HP,
(unsigned long)srng->u.dst_ring.tp_addr -
(unsigned long)ab->mem);
}
}
}
int ath12k_wifi7_hal_srng_get_ring_id(struct ath12k_hal *hal,
enum hal_ring_type type,
int ring_num, int mac_id)
{
struct hal_srng_config *srng_config = &hal->srng_config[type];
int ring_id;
if (ring_num >= srng_config->max_rings) {
ath12k_warn(hal, "invalid ring number :%d\n", ring_num);
return -EINVAL;
}
ring_id = srng_config->start_ring_id + ring_num;
if (srng_config->mac_type == ATH12K_HAL_SRNG_PMAC)
ring_id += mac_id * HAL_SRNG_RINGS_PER_PMAC;
if (WARN_ON(ring_id >= HAL_SRNG_RING_ID_MAX))
return -EINVAL;
return ring_id;
}
static
void ath12k_wifi7_hal_srng_update_hp_tp_addr(struct ath12k_base *ab,
int shadow_cfg_idx,
enum hal_ring_type ring_type,
int ring_num)
{
struct hal_srng *srng;
struct ath12k_hal *hal = &ab->hal;
int ring_id;
struct hal_srng_config *srng_config = &hal->srng_config[ring_type];
ring_id = ath12k_wifi7_hal_srng_get_ring_id(hal, ring_type, ring_num,
0);
if (ring_id < 0)
return;
srng = &hal->srng_list[ring_id];
if (srng_config->ring_dir == HAL_SRNG_DIR_DST)
srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +
(unsigned long)ab->mem);
else
srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) +
(unsigned long)ab->mem);
}
u32 ath12k_wifi7_hal_ce_get_desc_size(enum hal_ce_desc type)
{
switch (type) {
case HAL_CE_DESC_SRC:
return sizeof(struct hal_ce_srng_src_desc);
case HAL_CE_DESC_DST:
return sizeof(struct hal_ce_srng_dest_desc);
case HAL_CE_DESC_DST_STATUS:
return sizeof(struct hal_ce_srng_dst_status_desc);
}
return 0;
}
int ath12k_wifi7_hal_srng_update_shadow_config(struct ath12k_base *ab,
enum hal_ring_type ring_type,
int ring_num)
Annotation
- Immediate include surface: `hw.h`, `hal_desc.h`, `../hal.h`, `hal.h`, `hal_tx.h`, `../debug.h`, `../hif.h`, `hal_qcn9274.h`.
- Detected declarations: `function ath12k_wifi7_hal_init`, `function ath12k_wifi7_hal_reo1_ring_id_offset`, `function ath12k_wifi7_hal_reo1_ring_msi1_base_lsb_offset`, `function ath12k_wifi7_hal_reo1_ring_msi1_base_msb_offset`, `function ath12k_wifi7_hal_reo1_ring_msi1_data_offset`, `function ath12k_wifi7_hal_reo1_ring_base_msb_offset`, `function ath12k_wifi7_hal_reo1_ring_producer_int_setup_offset`, `function ath12k_wifi7_hal_reo1_ring_hp_addr_lsb_offset`, `function ath12k_wifi7_hal_reo1_ring_hp_addr_msb_offset`, `function ath12k_wifi7_hal_reo1_ring_misc_offset`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.