drivers/net/wireless/ath/ath5k/reset.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath5k/reset.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath5k/reset.c- Extension
.c- Size
- 37457 bytes
- Lines
- 1381
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/unaligned.hlinux/pci.hlinux/log2.hlinux/platform_device.hath5k.hreg.hdebug.h
Detected Declarations
function Copyrightfunction ath5k_hw_htoclockfunction ath5k_hw_clocktohfunction ath5k_hw_init_core_clockfunction ath5k_hw_set_sleep_clockfunction ath5k_hw_nic_resetfunction ath5k_hw_wisoc_resetfunction ath5k_hw_set_power_modefunction ath5k_hw_on_holdfunction ath5k_hw_nic_wakeupfunction ath5k_hw_tweak_initval_settingsfunction ath5k_hw_commit_eeprom_settingsfunction ath5k_hw_reset
Annotated Snippet
if (to_platform_device(ah->dev)->id == 0) {
if (mask & AR5K_RESET_CTL_PCU)
val |= AR5K_AR5312_RESET_WMAC0;
if (mask & AR5K_RESET_CTL_BASEBAND)
val |= AR5K_AR5312_RESET_BB0_COLD |
AR5K_AR5312_RESET_BB0_WARM;
} else {
if (mask & AR5K_RESET_CTL_PCU)
val |= AR5K_AR5312_RESET_WMAC1;
if (mask & AR5K_RESET_CTL_BASEBAND)
val |= AR5K_AR5312_RESET_BB1_COLD |
AR5K_AR5312_RESET_BB1_WARM;
}
}
/* Put BB/MAC into reset */
regval = ioread32(reg);
iowrite32(regval | val, reg);
regval = ioread32(reg);
udelay(100); /* NB: should be atomic */
/* Bring BB/MAC out of reset */
iowrite32(regval & ~val, reg);
regval = ioread32(reg);
/*
* Reset configuration register (for hw byte-swap). Note that this
* is only set for big endian. We do the necessary magic in
* AR5K_INIT_CFG.
*/
if ((flags & AR5K_RESET_CTL_PCU) == 0)
ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
return 0;
}
/**
* ath5k_hw_set_power_mode() - Set power mode
* @ah: The &struct ath5k_hw
* @mode: One of enum ath5k_power_mode
* @set_chip: Set to true to write sleep control register
* @sleep_duration: How much time the device is allowed to sleep
* when sleep logic is enabled (in 128 microsecond increments).
*
* This function is used to configure sleep policy and allowed
* sleep modes. For more information check out the sleep control
* register on reg.h and STA_ID1.
*
* Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
* mode is requested.
*/
static int
ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
bool set_chip, u16 sleep_duration)
{
unsigned int i;
u32 staid, data;
staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
switch (mode) {
case AR5K_PM_AUTO:
staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
fallthrough;
case AR5K_PM_NETWORK_SLEEP:
if (set_chip)
ath5k_hw_reg_write(ah,
AR5K_SLEEP_CTL_SLE_ALLOW |
sleep_duration,
AR5K_SLEEP_CTL);
staid |= AR5K_STA_ID1_PWR_SV;
break;
case AR5K_PM_FULL_SLEEP:
if (set_chip)
ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
AR5K_SLEEP_CTL);
staid |= AR5K_STA_ID1_PWR_SV;
break;
case AR5K_PM_AWAKE:
staid &= ~AR5K_STA_ID1_PWR_SV;
if (!set_chip)
goto commit;
data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
Annotation
- Immediate include surface: `linux/unaligned.h`, `linux/pci.h`, `linux/log2.h`, `linux/platform_device.h`, `ath5k.h`, `reg.h`, `debug.h`.
- Detected declarations: `function Copyright`, `function ath5k_hw_htoclock`, `function ath5k_hw_clocktoh`, `function ath5k_hw_init_core_clock`, `function ath5k_hw_set_sleep_clock`, `function ath5k_hw_nic_reset`, `function ath5k_hw_wisoc_reset`, `function ath5k_hw_set_power_mode`, `function ath5k_hw_on_hold`, `function ath5k_hw_nic_wakeup`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.