drivers/net/wireless/ath/ath9k/ar9002_phy.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath9k/ar9002_phy.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/ath/ath9k/ar9002_phy.h
Extension
.h
Size
23901 bytes
Lines
621
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef AR9002_PHY_H
#define AR9002_PHY_H

#define AR_PHY_TEST             0x9800
#define PHY_AGC_CLR             0x10000000
#define RFSILENT_BB             0x00002000

#define AR_PHY_TURBO                0x9804
#define AR_PHY_FC_TURBO_MODE        0x00000001
#define AR_PHY_FC_TURBO_SHORT       0x00000002
#define AR_PHY_FC_DYN2040_EN        0x00000004
#define AR_PHY_FC_DYN2040_PRI_ONLY  0x00000008
#define AR_PHY_FC_DYN2040_PRI_CH    0x00000010
/* For 25 MHz channel spacing -- not used but supported by hw */
#define AR_PHY_FC_DYN2040_EXT_CH    0x00000020
#define AR_PHY_FC_HT_EN             0x00000040
#define AR_PHY_FC_SHORT_GI_40       0x00000080
#define AR_PHY_FC_WALSH             0x00000100
#define AR_PHY_FC_SINGLE_HT_LTF1    0x00000200
#define AR_PHY_FC_ENABLE_DAC_FIFO   0x00000800

#define AR_PHY_TEST2			0x9808

#define AR_PHY_TIMING2           0x9810
#define AR_PHY_TIMING3           0x9814
#define AR_PHY_TIMING3_DSC_MAN   0xFFFE0000
#define AR_PHY_TIMING3_DSC_MAN_S 17
#define AR_PHY_TIMING3_DSC_EXP   0x0001E000
#define AR_PHY_TIMING3_DSC_EXP_S 13

#define AR_PHY_CHIP_ID_REV_0      0x80
#define AR_PHY_CHIP_ID_REV_1      0x81
#define AR_PHY_CHIP_ID_9160_REV_0 0xb0

#define AR_PHY_ACTIVE       0x981C
#define AR_PHY_ACTIVE_EN    0x00000001
#define AR_PHY_ACTIVE_DIS   0x00000000

#define AR_PHY_RF_CTL2             0x9824
#define AR_PHY_TX_END_DATA_START   0x000000FF
#define AR_PHY_TX_END_DATA_START_S 0
#define AR_PHY_TX_END_PA_ON        0x0000FF00
#define AR_PHY_TX_END_PA_ON_S      8

#define AR_PHY_RF_CTL3                  0x9828
#define AR_PHY_TX_END_TO_A2_RX_ON       0x00FF0000
#define AR_PHY_TX_END_TO_A2_RX_ON_S     16
#define AR_PHY_TX_END_TO_ADC_ON         0xFF000000
#define AR_PHY_TX_END_TO_ADC_ON_S       24

#define AR_PHY_ADC_CTL                  0x982C
#define AR_PHY_ADC_CTL_OFF_INBUFGAIN    0x00000003
#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S  0
#define AR_PHY_ADC_CTL_OFF_PWDDAC       0x00002000
#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP   0x00004000
#define AR_PHY_ADC_CTL_OFF_PWDADC       0x00008000
#define AR_PHY_ADC_CTL_ON_INBUFGAIN     0x00030000
#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S   16

#define AR_PHY_ADC_SERIAL_CTL       0x9830
#define AR_PHY_SEL_INTERNAL_ADDAC   0x00000000
#define AR_PHY_SEL_EXTERNAL_RADIO   0x00000001

#define AR_PHY_RF_CTL4                    0x9834
#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF    0xFF000000
#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S  24
#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF    0x00FF0000
#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S  16
#define AR_PHY_RF_CTL4_FRAME_XPAB_ON      0x0000FF00
#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S    8
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON      0x000000FF
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S    0

#define AR_PHY_TSTDAC_CONST               0x983c

#define AR_PHY_SETTLING          0x9844
#define AR_PHY_SETTLING_SWITCH   0x00003F80
#define AR_PHY_SETTLING_SWITCH_S 7

#define AR_PHY_RXGAIN                   0x9848
#define AR_PHY_RXGAIN_TXRX_ATTEN        0x0003F000
#define AR_PHY_RXGAIN_TXRX_ATTEN_S      12
#define AR_PHY_RXGAIN_TXRX_RF_MAX       0x007C0000
#define AR_PHY_RXGAIN_TXRX_RF_MAX_S     18
#define AR9280_PHY_RXGAIN_TXRX_ATTEN    0x00003F80
#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S  7
#define AR9280_PHY_RXGAIN_TXRX_MARGIN   0x001FC000
#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14

#define AR_PHY_DESIRED_SZ           0x9850

Annotation

Implementation Notes