drivers/net/wireless/ath/ath9k/ar9003_mac.h
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath9k/ar9003_mac.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath9k/ar9003_mac.h- Extension
.h- Size
- 3577 bytes
- Lines
- 124
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct ar9003_rxsstruct ar9003_txcstruct ar9003_txs
Annotated Snippet
struct ar9003_rxs {
u32 ds_info;
u32 status1;
u32 status2;
u32 status3;
u32 status4;
u32 status5;
u32 status6;
u32 status7;
u32 status8;
u32 status9;
u32 status10;
u32 status11;
} __packed __aligned(4);
/* Transmit Control Descriptor */
struct ar9003_txc {
u32 info; /* descriptor information */
u32 link; /* link pointer */
u32 data0; /* data pointer to 1st buffer */
u32 ctl3; /* DMA control 3 */
u32 data1; /* data pointer to 2nd buffer */
u32 ctl5; /* DMA control 5 */
u32 data2; /* data pointer to 3rd buffer */
u32 ctl7; /* DMA control 7 */
u32 data3; /* data pointer to 4th buffer */
u32 ctl9; /* DMA control 9 */
u32 ctl10; /* DMA control 10 */
u32 ctl11; /* DMA control 11 */
u32 ctl12; /* DMA control 12 */
u32 ctl13; /* DMA control 13 */
u32 ctl14; /* DMA control 14 */
u32 ctl15; /* DMA control 15 */
u32 ctl16; /* DMA control 16 */
u32 ctl17; /* DMA control 17 */
u32 ctl18; /* DMA control 18 */
u32 ctl19; /* DMA control 19 */
u32 ctl20; /* DMA control 20 */
u32 ctl21; /* DMA control 21 */
u32 ctl22; /* DMA control 22 */
u32 ctl23; /* DMA control 23 */
u32 pad[8]; /* pad to cache line (128 bytes/32 dwords) */
} __packed __aligned(4);
struct ar9003_txs {
u32 ds_info;
u32 status1;
u32 status2;
u32 status3;
u32 status4;
u32 status5;
u32 status6;
u32 status7;
u32 status8;
} __packed __aligned(4);
void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
enum ath9k_rx_qtype qtype);
int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
struct ath_rx_status *rxs,
void *buf_addr);
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
u32 ts_paddr_start,
u16 size);
#endif
Annotation
- Detected declarations: `struct ar9003_rxs`, `struct ar9003_txc`, `struct ar9003_txs`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.