drivers/net/wireless/ath/ath9k/ar9003_phy.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath9k/ar9003_phy.h

File Facts

System: Linux kernel
Corpus path: drivers/net/wireless/ath/ath9k/ar9003_phy.h
Extension: .h
Size: 59380 bytes
Lines: 1321
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef AR9003_PHY_H
#define AR9003_PHY_H

/*
 * Channel Register Map
 */
#define AR_CHAN_BASE	0x9800

#define AR_PHY_TIMING1      (AR_CHAN_BASE + 0x0)
#define AR_PHY_TIMING2      (AR_CHAN_BASE + 0x4)
#define AR_PHY_TIMING3      (AR_CHAN_BASE + 0x8)
#define AR_PHY_TIMING4      (AR_CHAN_BASE + 0xc)
#define AR_PHY_TIMING5      (AR_CHAN_BASE + 0x10)
#define AR_PHY_TIMING6      (AR_CHAN_BASE + 0x14)
#define AR_PHY_TIMING11     (AR_CHAN_BASE + 0x18)
#define AR_PHY_SPUR_REG     (AR_CHAN_BASE + 0x1c)
#define AR_PHY_RX_IQCAL_CORR_B0    (AR_CHAN_BASE + 0xdc)
#define AR_PHY_TX_IQCAL_CONTROL_3  (AR_CHAN_BASE + 0xb0)
#define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT 16

#define AR_PHY_TIMING11_SPUR_FREQ_SD    0x3FF00000
#define AR_PHY_TIMING11_SPUR_FREQ_SD_S  20

#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0

#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30

#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31

#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT         0x4000000
#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S       26

#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM                         0x20000     /* bins move with freq offset */
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S                       17
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH            0x000000FF
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S          0
#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI                        0x00000100
#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S                      8
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL                          0x03FC0000
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S			18

#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN   0x20000000
#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S         29

#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN   0x80000000
#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S         31

#define AR_PHY_FIND_SIG_LOW  (AR_CHAN_BASE + 0x20)

#define AR_PHY_SFCORR           (AR_CHAN_BASE + 0x24)
#define AR_PHY_SFCORR_LOW       (AR_CHAN_BASE + 0x28)
#define AR_PHY_SFCORR_EXT       (AR_CHAN_BASE + 0x2c)

#define AR_PHY_EXT_CCA              (AR_CHAN_BASE + 0x30)
#define AR_PHY_RADAR_0              (AR_CHAN_BASE + 0x34)
#define AR_PHY_RADAR_1              (AR_CHAN_BASE + 0x38)
#define AR_PHY_RADAR_EXT            (AR_CHAN_BASE + 0x3c)
#define AR_PHY_MULTICHAIN_CTRL      (AR_CHAN_BASE + 0x80)
#define AR_PHY_PERCHAIN_CSD         (AR_CHAN_BASE + 0x84)

#define AR_PHY_TX_PHASE_RAMP_0      (AR_CHAN_BASE + 0xd0)
#define AR_PHY_ADC_GAIN_DC_CORR_0   (AR_CHAN_BASE + 0xd4)
#define AR_PHY_IQ_ADC_MEAS_0_B0     (AR_CHAN_BASE + 0xc0)
#define AR_PHY_IQ_ADC_MEAS_1_B0     (AR_CHAN_BASE + 0xc4)
#define AR_PHY_IQ_ADC_MEAS_2_B0     (AR_CHAN_BASE + 0xc8)
#define AR_PHY_IQ_ADC_MEAS_3_B0     (AR_CHAN_BASE + 0xcc)

/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
#define AR_PHY_TX_PHASE_RAMP_0_9300_10      (AR_CHAN_BASE + 0xd0 - 0x10)
#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10   (AR_CHAN_BASE + 0xd4 - 0x10)
#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10     (AR_CHAN_BASE + 0xc0 + 0x8)
#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10     (AR_CHAN_BASE + 0xc4 + 0x8)
#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10     (AR_CHAN_BASE + 0xc8 + 0x8)
#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10     (AR_CHAN_BASE + 0xcc + 0x8)

#define AR_PHY_TX_CRC               (AR_CHAN_BASE + 0xa0)
#define AR_PHY_TST_DAC_CONST        (AR_CHAN_BASE + 0xa4)
#define AR_PHY_SPUR_REPORT_0        (AR_CHAN_BASE + 0xa8)
#define AR_PHY_CHAN_INFO_TAB_0      (AR_CHAN_BASE + 0x300)

/*
 * Channel Field Definitions
 */
#define AR_PHY_TIMING2_USE_FORCE_PPM    0x00001000
#define AR_PHY_TIMING2_FORCE_PPM_VAL    0x00000fff
#define AR_PHY_TIMING3_DSC_MAN      0xFFFE0000
#define AR_PHY_TIMING3_DSC_MAN_S    17

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.