drivers/net/wireless/ath/ath9k/ath9k.h
Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath9k/ath9k.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/ath/ath9k/ath9k.h- Extension
.h- Size
- 31787 bytes
- Lines
- 1157
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/etherdevice.hlinux/device.hlinux/interrupt.hlinux/kstrtox.hlinux/leds.hlinux/completion.hlinux/time.hlinux/hw_random.hcommon.hdebug.hmci.hdfs.h
Detected Declarations
struct ath_nodestruct ath_vifstruct ath_descdmastruct ath_txqstruct ath_frame_infostruct ath_rxbufstruct ath_buf_statestruct ath_bufstruct ath_atx_tidstruct ath_nodestruct ath_tx_controlstruct ath_txstruct ath_rx_edmastruct ath_rxstruct ath_acqstruct ath_chanctxstruct ath_chanctx_schedstruct ath_offchannelstruct ath_vifstruct ath9k_vif_iter_datastruct ath_beaconstruct ath_btcoexstruct ath_ant_combstruct ath_softcenum buffer_typeenum ath_chanctx_eventenum ath_chanctx_stateenum ath_offchannel_stateenum ath_roc_complete_reasonenum bt_op_flagsfunction ath_node_to_tidfunction ath_chanctx_getfunction ath9k_is_chanctx_enabledfunction ath9k_fill_chanctx_opsfunction ath9k_deinit_p2pfunction ath_txq_unlockfunction ath9k_init_btcoexfunction ath9k_deinit_btcoexfunction ath9k_btcoex_stop_gen_timerfunction ath_init_ledsfunction ath9k_init_wowfunction ath9k_resumefunction ath9k_set_wakeupfunction ath9k_tx99_init_debugfunction ath9k_rng_startfunction ath_pci_initfunction ath_pci_exitfunction ath_ahb_init
Annotated Snippet
struct ath_descdma {
void *dd_desc;
dma_addr_t dd_desc_paddr;
u32 dd_desc_len;
};
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
struct list_head *head, const char *name,
int nbuf, int ndesc, bool is_tx);
/***********/
/* RX / TX */
/***********/
#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
/* increment with wrap-around */
#define INCR(_l, _sz) do { \
(_l)++; \
(_l) &= ((_sz) - 1); \
} while (0)
#define ATH_RXBUF 512
#define ATH_TXBUF 512
#define ATH_TXBUF_RESERVE 5
#define ATH_TXMAXTRY 13
#define ATH_MAX_SW_RETRIES 30
#define TID_TO_WME_AC(_tid) \
((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
(((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
(((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
IEEE80211_AC_VO)
#define ATH_AGGR_DELIM_SZ 4
#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
/* number of delimiters for encryption padding */
#define ATH_AGGR_ENCRYPTDELIM 10
/* minimum h/w qdepth to be sustained to maximize aggregation */
#define ATH_AGGR_MIN_QDEPTH 2
/* minimum h/w qdepth for non-aggregated traffic */
#define ATH_NON_AGGR_MIN_QDEPTH 8
#define ATH_HW_CHECK_POLL_INT 1000
#define ATH_TXFIFO_DEPTH 8
#define ATH_TX_ERROR 0x01
/* Stop tx traffic 1ms before the GO goes away */
#define ATH_P2P_PS_STOP_TIME 1000
#define IEEE80211_SEQ_SEQ_SHIFT 4
#define IEEE80211_SEQ_MAX 4096
#define IEEE80211_WEP_IVLEN 3
#define IEEE80211_WEP_KIDLEN 1
#define IEEE80211_WEP_CRCLEN 4
#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
(IEEE80211_WEP_IVLEN + \
IEEE80211_WEP_KIDLEN + \
IEEE80211_WEP_CRCLEN))
/* return whether a bit at index _n in bitmap _bm is set
* _sz is the size of the bitmap */
#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
/* return block-ack bitmap index given sequence and starting sequence */
#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
/* return the seqno for _start + _offset */
#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
/* returns delimiter padding required given the packet length */
#define ATH_AGGR_GET_NDELIM(_len) \
(((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
#define BAW_WITHIN(_start, _bawsz, _seqno) \
((((_seqno) - (_start)) & 4095) < (_bawsz))
#define ATH_AN_2_TID(_an, _tidno) ath_node_to_tid(_an, _tidno)
#define IS_HT_RATE(rate) (rate & 0x80)
#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
#define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
enum {
WLAN_RC_PHY_OFDM,
WLAN_RC_PHY_CCK,
};
struct ath_txq {
Annotation
- Immediate include surface: `linux/etherdevice.h`, `linux/device.h`, `linux/interrupt.h`, `linux/kstrtox.h`, `linux/leds.h`, `linux/completion.h`, `linux/time.h`, `linux/hw_random.h`.
- Detected declarations: `struct ath_node`, `struct ath_vif`, `struct ath_descdma`, `struct ath_txq`, `struct ath_frame_info`, `struct ath_rxbuf`, `struct ath_buf_state`, `struct ath_buf`, `struct ath_atx_tid`, `struct ath_node`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.