drivers/net/wireless/ath/ath9k/reg_aic.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath9k/reg_aic.h

File Facts

System: Linux kernel
Corpus path: drivers/net/wireless/ath/ath9k/reg_aic.h
Extension: .h
Size: 8498 bytes
Lines: 165
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef REG_AIC_H
#define REG_AIC_H

#define AR_PHY_AIC_CTRL_0_B0                    (AR_SM_BASE + 0x4b0)
#define AR_PHY_AIC_CTRL_1_B0                    (AR_SM_BASE + 0x4b4)
#define AR_PHY_AIC_CTRL_2_B0                    (AR_SM_BASE + 0x4b8)
#define AR_PHY_AIC_CTRL_3_B0                    (AR_SM_BASE + 0x4bc)
#define AR_PHY_AIC_CTRL_4_B0                    (AR_SM_BASE + 0x4c0)

#define AR_PHY_AIC_STAT_0_B0                    (AR_SM_BASE + 0x4c4)
#define AR_PHY_AIC_STAT_1_B0                    (AR_SM_BASE + 0x4c8)
#define AR_PHY_AIC_STAT_2_B0                    (AR_SM_BASE + 0x4cc)

#define AR_PHY_AIC_CTRL_0_B1                    (AR_SM1_BASE + 0x4b0)
#define AR_PHY_AIC_CTRL_1_B1                    (AR_SM1_BASE + 0x4b4)
#define AR_PHY_AIC_CTRL_4_B1                    (AR_SM1_BASE + 0x4c0)

#define AR_PHY_AIC_STAT_0_B1                    (AR_SM1_BASE + 0x4c4)
#define AR_PHY_AIC_STAT_1_B1                    (AR_SM1_BASE + 0x4c8)
#define AR_PHY_AIC_STAT_2_B1                    (AR_SM1_BASE + 0x4cc)

#define AR_PHY_AIC_SRAM_ADDR_B0                 (AR_SM_BASE + 0x5f0)
#define AR_PHY_AIC_SRAM_DATA_B0                 (AR_SM_BASE + 0x5f4)

#define AR_PHY_AIC_SRAM_ADDR_B1                 (AR_SM1_BASE + 0x5f0)
#define AR_PHY_AIC_SRAM_DATA_B1                 (AR_SM1_BASE + 0x5f4)

#define AR_PHY_BT_COEX_4                        (AR_AGC_BASE + 0x60)
#define AR_PHY_BT_COEX_5                        (AR_AGC_BASE + 0x64)

/* AIC fields */
#define AR_PHY_AIC_MON_ENABLE                   0x80000000
#define AR_PHY_AIC_MON_ENABLE_S                 31
#define AR_PHY_AIC_CAL_MAX_HOP_COUNT            0x7F000000
#define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S          24
#define AR_PHY_AIC_CAL_MIN_VALID_COUNT          0x00FE0000
#define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S        17
#define AR_PHY_AIC_F_WLAN                       0x0001FC00
#define AR_PHY_AIC_F_WLAN_S                     10
#define AR_PHY_AIC_CAL_CH_VALID_RESET           0x00000200
#define AR_PHY_AIC_CAL_CH_VALID_RESET_S         9
#define AR_PHY_AIC_CAL_ENABLE                   0x00000100
#define AR_PHY_AIC_CAL_ENABLE_S                 8
#define AR_PHY_AIC_BTTX_PWR_THR                 0x000000FE
#define AR_PHY_AIC_BTTX_PWR_THR_S               1
#define AR_PHY_AIC_ENABLE                       0x00000001
#define AR_PHY_AIC_ENABLE_S                     0
#define AR_PHY_AIC_CAL_BT_REF_DELAY             0x00F00000
#define AR_PHY_AIC_CAL_BT_REF_DELAY_S           20
#define AR_PHY_AIC_BT_IDLE_CFG                  0x00080000
#define AR_PHY_AIC_BT_IDLE_CFG_S                19
#define AR_PHY_AIC_STDBY_COND                   0x00060000
#define AR_PHY_AIC_STDBY_COND_S                 17
#define AR_PHY_AIC_STDBY_ROT_ATT_DB             0x0001F800
#define AR_PHY_AIC_STDBY_ROT_ATT_DB_S           11
#define AR_PHY_AIC_STDBY_COM_ATT_DB             0x00000700
#define AR_PHY_AIC_STDBY_COM_ATT_DB_S           8
#define AR_PHY_AIC_RSSI_MAX                     0x000000F0
#define AR_PHY_AIC_RSSI_MAX_S                   4
#define AR_PHY_AIC_RSSI_MIN                     0x0000000F
#define AR_PHY_AIC_RSSI_MIN_S                   0
#define AR_PHY_AIC_RADIO_DELAY                  0x7F000000
#define AR_PHY_AIC_RADIO_DELAY_S                24
#define AR_PHY_AIC_CAL_STEP_SIZE_CORR           0x00F00000
#define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S         20
#define AR_PHY_AIC_CAL_ROT_IDX_CORR             0x000F8000
#define AR_PHY_AIC_CAL_ROT_IDX_CORR_S           15
#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR        0x00006000
#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S      13
#define AR_PHY_AIC_ROT_IDX_COUNT_MAX            0x00001C00
#define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S          10
#define AR_PHY_AIC_CAL_SYNTH_TOGGLE             0x00000200
#define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S           9
#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX         0x00000100
#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S       8
#define AR_PHY_AIC_CAL_SYNTH_SETTLING           0x000000FF
#define AR_PHY_AIC_CAL_SYNTH_SETTLING_S         0
#define AR_PHY_AIC_MON_MAX_HOP_COUNT            0x07F00000
#define AR_PHY_AIC_MON_MAX_HOP_COUNT_S          20
#define AR_PHY_AIC_MON_MIN_STALE_COUNT          0x000FE000
#define AR_PHY_AIC_MON_MIN_STALE_COUNT_S        13
#define AR_PHY_AIC_MON_PWR_EST_LONG             0x00001000
#define AR_PHY_AIC_MON_PWR_EST_LONG_S           12
#define AR_PHY_AIC_MON_PD_TALLY_SCALING         0x00000C00
#define AR_PHY_AIC_MON_PD_TALLY_SCALING_S       10
#define AR_PHY_AIC_MON_PERF_THR                 0x000003E0
#define AR_PHY_AIC_MON_PERF_THR_S               5
#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING       0x00000018
#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S     3
#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR        0x00000006

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.