drivers/net/wireless/ath/ath9k/reg_mci.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/ath9k/reg_mci.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/ath/ath9k/reg_mci.h
Extension
.h
Size
16834 bytes
Lines
311
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef REG_MCI_H
#define REG_MCI_H

#define AR_MCI_COMMAND0                                 0x1800
#define AR_MCI_COMMAND0_HEADER                          0xFF
#define AR_MCI_COMMAND0_HEADER_S                        0
#define AR_MCI_COMMAND0_LEN                             0x1f00
#define AR_MCI_COMMAND0_LEN_S                           8
#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP               0x2000
#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S             13

#define AR_MCI_COMMAND1                                 0x1804

#define AR_MCI_COMMAND2                                 0x1808
#define AR_MCI_COMMAND2_RESET_TX                        0x01
#define AR_MCI_COMMAND2_RESET_TX_S                      0
#define AR_MCI_COMMAND2_RESET_RX                        0x02
#define AR_MCI_COMMAND2_RESET_RX_S                      1
#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES             0x3FC
#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S           2
#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP                0x400
#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S              10

#define AR_MCI_RX_CTRL                                  0x180c

#define AR_MCI_TX_CTRL                                  0x1810
/*
 * 0 = no division,
 * 1 = divide by 2,
 * 2 = divide by 4,
 * 3 = divide by 8
 */
#define AR_MCI_TX_CTRL_CLK_DIV                          0x03
#define AR_MCI_TX_CTRL_CLK_DIV_S                        0
#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE               0x04
#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S             2
#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ                 0xFFFFF8
#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S               3
#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM                  0xF000000
#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S                24

#define AR_MCI_MSG_ATTRIBUTES_TABLE                     0x1814
#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM            0xFFFF
#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S          0
#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR         0xFFFF0000
#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S       16

#define AR_MCI_SCHD_TABLE_0                             0x1818
#define AR_MCI_SCHD_TABLE_1                             0x181c
#define AR_MCI_GPM_0                                    0x1820
#define AR_MCI_GPM_1                                    0x1824
#define AR_MCI_GPM_WRITE_PTR                            0xFFFF0000
#define AR_MCI_GPM_WRITE_PTR_S                          16
#define AR_MCI_GPM_BUF_LEN                              0x0000FFFF
#define AR_MCI_GPM_BUF_LEN_S                            0

#define AR_MCI_INTERRUPT_RAW                            0x1828

#define AR_MCI_INTERRUPT_EN                             0x182c
#define AR_MCI_INTERRUPT_SW_MSG_DONE                    0x00000001
#define AR_MCI_INTERRUPT_SW_MSG_DONE_S                  0
#define AR_MCI_INTERRUPT_CPU_INT_MSG                    0x00000002
#define AR_MCI_INTERRUPT_CPU_INT_MSG_S                  1
#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL                  0x00000004
#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S                2
#define AR_MCI_INTERRUPT_RX_INVALID_HDR                 0x00000008
#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S               3
#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL                 0x00000010
#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S               4
#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL                 0x00000020
#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S               5
#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL                 0x00000080
#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S               7
#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL                 0x00000100
#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S               8
#define AR_MCI_INTERRUPT_RX_MSG                         0x00000200
#define AR_MCI_INTERRUPT_RX_MSG_S                       9
#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE            0x00000400
#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S          10
#define AR_MCI_INTERRUPT_BT_PRI                         0x07fff800
#define AR_MCI_INTERRUPT_BT_PRI_S                       11
#define AR_MCI_INTERRUPT_BT_PRI_THRESH                  0x08000000
#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S                27
#define AR_MCI_INTERRUPT_BT_FREQ                        0x10000000
#define AR_MCI_INTERRUPT_BT_FREQ_S                      28
#define AR_MCI_INTERRUPT_BT_STOMP                       0x20000000
#define AR_MCI_INTERRUPT_BT_STOMP_S                     29
#define AR_MCI_INTERRUPT_BB_AIC_IRQ                     0x40000000
#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S                   30
#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT              0x80000000

Annotation

Implementation Notes