drivers/net/wireless/ath/carl9170/phy.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/ath/carl9170/phy.h

File Facts

System: Linux kernel
Corpus path: drivers/net/wireless/ath/carl9170/phy.h
Extension: .h
Size: 25507 bytes
Lines: 565
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __CARL9170_SHARED_PHY_H
#define __CARL9170_SHARED_PHY_H

#define	AR9170_PHY_REG_BASE			(0x1bc000 + 0x9800)
#define	AR9170_PHY_REG(_n)			(AR9170_PHY_REG_BASE + \
						 ((_n) << 2))

#define	AR9170_PHY_REG_TEST			(AR9170_PHY_REG_BASE + 0x0000)
#define		AR9170_PHY_TEST_AGC_CLR			0x10000000
#define		AR9170_PHY_TEST_RFSILENT_BB		0x00002000

#define	AR9170_PHY_REG_TURBO			(AR9170_PHY_REG_BASE + 0x0004)
#define		AR9170_PHY_TURBO_FC_TURBO_MODE		0x00000001
#define		AR9170_PHY_TURBO_FC_TURBO_SHORT		0x00000002
#define		AR9170_PHY_TURBO_FC_DYN2040_EN		0x00000004
#define		AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY	0x00000008
#define		AR9170_PHY_TURBO_FC_DYN2040_PRI_CH	0x00000010
/* For 25 MHz channel spacing -- not used but supported by hw */
#define		AR9170_PHY_TURBO_FC_DYN2040_EXT_CH	0x00000020
#define		AR9170_PHY_TURBO_FC_HT_EN		0x00000040
#define		AR9170_PHY_TURBO_FC_SHORT_GI_40		0x00000080
#define		AR9170_PHY_TURBO_FC_WALSH		0x00000100
#define		AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1	0x00000200
#define		AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO	0x00000800

#define	AR9170_PHY_REG_TEST2			(AR9170_PHY_REG_BASE + 0x0008)

#define	AR9170_PHY_REG_TIMING2			(AR9170_PHY_REG_BASE + 0x0010)
#define		AR9170_PHY_TIMING2_USE_FORCE		0x00001000
#define		AR9170_PHY_TIMING2_FORCE		0x00000fff
#define		AR9170_PHY_TIMING2_FORCE_S			 0

#define	AR9170_PHY_REG_TIMING3			(AR9170_PHY_REG_BASE + 0x0014)
#define		AR9170_PHY_TIMING3_DSC_EXP		0x0001e000
#define		AR9170_PHY_TIMING3_DSC_EXP_S		13
#define		AR9170_PHY_TIMING3_DSC_MAN		0xfffe0000
#define		AR9170_PHY_TIMING3_DSC_MAN_S		17

#define	AR9170_PHY_REG_CHIP_ID			(AR9170_PHY_REG_BASE + 0x0018)
#define		AR9170_PHY_CHIP_ID_REV_0		0x80
#define		AR9170_PHY_CHIP_ID_REV_1		0x81
#define		AR9170_PHY_CHIP_ID_9160_REV_0		0xb0

#define	AR9170_PHY_REG_ACTIVE			(AR9170_PHY_REG_BASE + 0x001c)
#define		AR9170_PHY_ACTIVE_EN			0x00000001
#define		AR9170_PHY_ACTIVE_DIS			0x00000000

#define	AR9170_PHY_REG_RF_CTL2			(AR9170_PHY_REG_BASE + 0x0024)
#define		AR9170_PHY_RF_CTL2_TX_END_DATA_START	0x000000ff
#define		AR9170_PHY_RF_CTL2_TX_END_DATA_START_S	0
#define		AR9170_PHY_RF_CTL2_TX_END_PA_ON		0x0000ff00
#define		AR9170_PHY_RF_CTL2_TX_END_PA_ON_S	8

#define	AR9170_PHY_REG_RF_CTL3                  (AR9170_PHY_REG_BASE + 0x0028)
#define		AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON	0x00ff0000
#define		AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S	16

#define	AR9170_PHY_REG_ADC_CTL			(AR9170_PHY_REG_BASE + 0x002c)
#define		AR9170_PHY_ADC_CTL_OFF_INBUFGAIN	0x00000003
#define		AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S	0
#define		AR9170_PHY_ADC_CTL_OFF_PWDDAC		0x00002000
#define		AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP	0x00004000
#define		AR9170_PHY_ADC_CTL_OFF_PWDADC		0x00008000
#define		AR9170_PHY_ADC_CTL_ON_INBUFGAIN		0x00030000
#define		AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S	16

#define	AR9170_PHY_REG_ADC_SERIAL_CTL		(AR9170_PHY_REG_BASE + 0x0030)
#define		AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC	0x00000000
#define		AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO	0x00000001

#define	AR9170_PHY_REG_RF_CTL4			(AR9170_PHY_REG_BASE + 0x0034)
#define		AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF	0xff000000
#define		AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S	24
#define		AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF	0x00ff0000
#define		AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S	16
#define		AR9170_PHY_RF_CTL4_FRAME_XPAB_ON	0x0000ff00
#define		AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S	8
#define		AR9170_PHY_RF_CTL4_FRAME_XPAA_ON	0x000000ff
#define		AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S	0

#define	AR9170_PHY_REG_TSTDAC_CONST		(AR9170_PHY_REG_BASE + 0x003c)

#define	AR9170_PHY_REG_SETTLING			(AR9170_PHY_REG_BASE + 0x0044)
#define		AR9170_PHY_SETTLING_SWITCH		0x00003f80
#define		AR9170_PHY_SETTLING_SWITCH_S		7

#define	AR9170_PHY_REG_RXGAIN			(AR9170_PHY_REG_BASE + 0x0048)
#define	AR9170_PHY_REG_RXGAIN_CHAIN_2		(AR9170_PHY_REG_BASE + 0x2048)
#define		AR9170_PHY_RXGAIN_TXRX_ATTEN		0x0003f000
#define		AR9170_PHY_RXGAIN_TXRX_ATTEN_S		12

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.