drivers/net/wireless/broadcom/b43/phy_g.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/broadcom/b43/phy_g.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/broadcom/b43/phy_g.c- Extension
.c- Size
- 82907 bytes
- Lines
- 3058
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
b43.hphy_g.hphy_common.hlo.hmain.hwa.hlinux/bitrev.hlinux/slab.h
Detected Declarations
struct init2050_saved_valuesfunction channel2freq_bgfunction generate_rfatt_listfunction generate_bbatt_listfunction b43_shm_clear_tssifunction b43_synth_pu_workaroundfunction b43_gphy_set_baseband_attenuationfunction b43_set_txpower_gfunction b43_gphy_tssi_power_lt_initfunction b43_gphy_gain_lt_initfunction b43_set_all_gainsfunction b43_set_original_gainsfunction b43_nrssi_hw_writefunction b43_nrssi_hw_readfunction b43_nrssi_hw_updatefunction b43_nrssi_mem_updatefunction b43_calc_nrssi_offsetfunction b43_calc_nrssi_slopefunction b43_calc_nrssi_thresholdfunction _stack_savefunction _stack_restorefunction b43_radio_interference_mitigation_enablefunction b43_radio_interference_mitigation_disablefunction b43_radio_core_calibration_valuefunction radio2050_rfover_valfunction b43_radio_init2050function b43_phy_initb5function b43_phy_initb6function b43_calc_loopback_gainfunction b43_hardware_pctl_early_initfunction b43_hardware_pctl_init_gphyfunction b43_phy_init_pctlfunction b43_phy_initafunction b43_phy_initgfunction b43_gphy_channel_switchfunction default_baseband_attenuationfunction default_radio_attenuationfunction default_tx_controlfunction b43_gphy_aci_detectfunction b43_gphy_aci_scanfunction b43_tssi2dbm_adfunction b43_tssi2dbm_entryfunction b43_gphy_init_tssi2dbm_tablefunction b43_gphy_op_allocatefunction b43_gphy_op_prepare_structsfunction b43_gphy_op_freefunction b43_gphy_op_prepare_hardwarefunction b43_gphy_op_init
Annotated Snippet
struct init2050_saved_values {
/* Core registers */
u16 reg_3EC;
u16 reg_3E6;
u16 reg_3F4;
/* Radio registers */
u16 radio_43;
u16 radio_51;
u16 radio_52;
/* PHY registers */
u16 phy_pgactl;
u16 phy_cck_5A;
u16 phy_cck_59;
u16 phy_cck_58;
u16 phy_cck_30;
u16 phy_rfover;
u16 phy_rfoverval;
u16 phy_analogover;
u16 phy_analogoverval;
u16 phy_crs0;
u16 phy_classctl;
u16 phy_lo_mask;
u16 phy_lo_ctl;
u16 phy_syncctl;
};
static u16 b43_radio_init2050(struct b43_wldev *dev)
{
struct b43_phy *phy = &dev->phy;
struct init2050_saved_values sav;
u16 rcc;
u16 radio78;
u16 ret;
u16 i, j;
u32 tmp1 = 0, tmp2 = 0;
memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
sav.radio_43 = b43_radio_read16(dev, 0x43);
sav.radio_51 = b43_radio_read16(dev, 0x51);
sav.radio_52 = b43_radio_read16(dev, 0x52);
sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
if (phy->type == B43_PHYTYPE_B) {
sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
sav.reg_3EC = b43_read16(dev, 0x3EC);
b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
b43_write16(dev, 0x3EC, 0x3F3F);
} else if (phy->gmode || phy->rev >= 2) {
sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
sav.phy_analogoverval =
b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
if (has_loopback_gain(phy)) {
sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
if (phy->rev >= 3)
b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
else
b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
b43_phy_write(dev, B43_PHY_LO_CTL, 0);
}
b43_phy_write(dev, B43_PHY_RFOVERVAL,
radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
LPD(0, 1, 1)));
b43_phy_write(dev, B43_PHY_RFOVER,
radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
}
b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
sav.reg_3E6 = b43_read16(dev, 0x3E6);
sav.reg_3F4 = b43_read16(dev, 0x3F4);
if (phy->analog == 0) {
Annotation
- Immediate include surface: `b43.h`, `phy_g.h`, `phy_common.h`, `lo.h`, `main.h`, `wa.h`, `linux/bitrev.h`, `linux/slab.h`.
- Detected declarations: `struct init2050_saved_values`, `function channel2freq_bg`, `function generate_rfatt_list`, `function generate_bbatt_list`, `function b43_shm_clear_tssi`, `function b43_synth_pu_workaround`, `function b43_gphy_set_baseband_attenuation`, `function b43_set_txpower_g`, `function b43_gphy_tssi_power_lt_init`, `function b43_gphy_gain_lt_init`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.