drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h
Extension
.h
Size
9998 bytes
Lines
295
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _BRCM_TYPES_H_
#define _BRCM_TYPES_H_

#include <linux/types.h>
#include <linux/io.h>

#define WL_CHAN_FREQ_RANGE_2G      0
#define WL_CHAN_FREQ_RANGE_5GL     1
#define WL_CHAN_FREQ_RANGE_5GM     2
#define WL_CHAN_FREQ_RANGE_5GH     3

/* boardflags */

/* Board has gpio 9 controlling the PA */
#define	BFL_PACTRL		0x00000002
/* Not ok to power down the chip pll and oscillator */
#define	BFL_NOPLLDOWN		0x00000020
/* Board supports the Front End Module */
#define BFL_FEM			0x00000800
/* Board has an external LNA in 2.4GHz band */
#define BFL_EXTLNA		0x00001000
/* Board has no PA */
#define BFL_NOPA		0x00010000
/* Power topology uses BUCKBOOST */
#define BFL_BUCKBOOST		0x00200000
/* Board has FEM and switch to share antenna w/ BT */
#define BFL_FEM_BT		0x00400000
/* Power topology doesn't use CBUCK */
#define BFL_NOCBUCK		0x00800000
/* Power topology uses PALDO */
#define BFL_PALDO		0x02000000
/* Board has an external LNA in 5GHz band */
#define BFL_EXTLNA_5GHz		0x10000000

/* boardflags2 */

/* Board has an external rxbb regulator */
#define BFL2_RXBB_INT_REG_DIS	0x00000001
/* Flag to implement alternative A-band PLL settings */
#define BFL2_APLL_WAR		0x00000002
/* Board permits enabling TX Power Control */
#define BFL2_TXPWRCTRL_EN	0x00000004
/* Board supports the 2X4 diversity switch */
#define BFL2_2X4_DIV		0x00000008
/* Board supports 5G band power gain */
#define BFL2_5G_PWRGAIN		0x00000010
/* Board overrides ASPM and Clkreq settings */
#define BFL2_PCIEWAR_OVR	0x00000020
#define BFL2_LEGACY		0x00000080
/* 4321mcm93 board uses Skyworks FEM */
#define BFL2_SKWRKFEM_BRD	0x00000100
/* Board has a WAR for clock-harmonic spurs */
#define BFL2_SPUR_WAR		0x00000200
/* Flag to narrow G-band PLL loop b/w */
#define BFL2_GPLL_WAR		0x00000400
/* Tx CCK pkts on Ant 0 only */
#define BFL2_SINGLEANT_CCK	0x00001000
/* WAR to reduce and avoid clock-harmonic spurs in 2G */
#define BFL2_2G_SPUR_WAR	0x00002000
/* Flag to widen G-band PLL loop b/w */
#define BFL2_GPLL_WAR2	        0x00010000
#define BFL2_IPALVLSHIFT_3P3    0x00020000
/* Use internal envelope detector for TX IQCAL */
#define BFL2_INTERNDET_TXIQCAL  0x00040000
/* Keep the buffered Xtal output from radio "ON". Most drivers will turn it
 * off without this flag to save power. */
#define BFL2_XTALBUFOUTEN       0x00080000

/*
 * board specific GPIO assignment, gpio 0-3 are also customer-configurable
 * led
 */

/* bit 9 controls the PA on new 4306 boards */
#define	BOARD_GPIO_PACTRL	0x200
#define BOARD_GPIO_12		0x1000
#define BOARD_GPIO_13		0x2000

/* **** Core type/rev defaults **** */
#define D11CONF		0x0fffffb0	/* Supported  D11 revs: 4, 5, 7-27
					 * also need to update wlc.h MAXCOREREV
					 */

#define NCONF		0x000001ff	/* Supported nphy revs:
					 *      0       4321a0
					 *      1       4321a1
					 *      2       4321b0/b1/c0/c1
					 *      3       4322a0
					 *      4       4322a1
					 *      5       4716a0

Annotation

Implementation Notes