drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-v2.c- Extension
.c- Size
- 18297 bytes
- Lines
- 619
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dmi.hiwl-trans.hiwl-fh.hiwl-context-info-v2.hgen1_2/internal.hiwl-prph.h
Detected Declarations
function iwl_is_force_scu_active_approvedfunction iwl_pcie_ctxt_info_dbg_enablefunction iwl_pcie_ctxt_info_v2_allocfunction iwl_pcie_ctxt_info_v2_kickfunction iwl_pcie_ctxt_info_v2_freefunction iwl_pcie_load_payloads_contigfunction iwl_pcie_load_payloads_segmentsfunction iwl_trans_pcie_ctx_info_v2_load_pnvmfunction iwl_dram_regions_sizefunction iwl_pcie_set_pnvm_segmentsfunction iwl_pcie_set_contig_pnvmfunction iwl_trans_pcie_ctx_info_v2_set_pnvmfunction iwl_trans_pcie_ctx_info_v2_load_reduce_powerfunction iwl_pcie_set_reduce_power_segmentsfunction iwl_pcie_set_contig_reduce_powerfunction iwl_trans_pcie_ctx_info_v2_set_reduce_power
Annotated Snippet
if (fw_mon->size) {
dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
IWL_DEBUG_FW(trans,
"WRT: Applying DRAM buffer destination\n");
dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
}
goto out;
}
fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
case IWL_FW_INI_LOCATION_SRAM_PATH:
dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
IWL_DEBUG_FW(trans,
"WRT: Applying SMEM buffer destination\n");
break;
case IWL_FW_INI_LOCATION_NPK_PATH:
dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
IWL_DEBUG_FW(trans,
"WRT: Applying NPK buffer destination\n");
break;
case IWL_FW_INI_LOCATION_DRAM_PATH:
if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
struct iwl_dram_data *frag =
&trans->dbg.fw_mon_ini[alloc_id].frags[0];
dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
dbg_cfg->hwm_size = cpu_to_le32(frag->size);
dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset);
IWL_DEBUG_FW(trans,
"WRT: Applying DRAM destination (debug_token_config=%u)\n",
dbg_cfg->debug_token_config);
IWL_DEBUG_FW(trans,
"WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
alloc_id,
trans->dbg.fw_mon_ini[alloc_id].num_frags);
}
break;
default:
IWL_DEBUG_FW(trans, "WRT: Invalid buffer destination (%d)\n",
le32_to_cpu(fw_mon_cfg->buf_location));
}
out:
if (dbg_flags)
*control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
}
int iwl_pcie_ctxt_info_v2_alloc(struct iwl_trans *trans,
const struct iwl_fw *fw,
const struct fw_img *img)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
struct iwl_context_info_v2 *ctxt_info_v2;
struct iwl_prph_scratch *prph_scratch;
struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
struct iwl_prph_info *prph_info;
u32 control_flags = 0;
u32 control_flags_ext = 0;
int ret;
int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
trans->mac_cfg->base->min_txq_size);
switch (trans->conf.rx_buf_size) {
case IWL_AMSDU_DEF:
return -EINVAL;
case IWL_AMSDU_2K:
break;
case IWL_AMSDU_4K:
control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
break;
case IWL_AMSDU_8K:
control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
/* if firmware supports the ext size, tell it */
control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
break;
case IWL_AMSDU_12K:
control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
/* if firmware supports the ext size, tell it */
control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K;
break;
}
if (trans->conf.dsbr_urm_fw_dependent)
Annotation
- Immediate include surface: `linux/dmi.h`, `iwl-trans.h`, `iwl-fh.h`, `iwl-context-info-v2.h`, `gen1_2/internal.h`, `iwl-prph.h`.
- Detected declarations: `function iwl_is_force_scu_active_approved`, `function iwl_pcie_ctxt_info_dbg_enable`, `function iwl_pcie_ctxt_info_v2_alloc`, `function iwl_pcie_ctxt_info_v2_kick`, `function iwl_pcie_ctxt_info_v2_free`, `function iwl_pcie_load_payloads_contig`, `function iwl_pcie_load_payloads_segments`, `function iwl_trans_pcie_ctx_info_v2_load_pnvm`, `function iwl_dram_regions_size`, `function iwl_pcie_set_pnvm_segments`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.